Refined statistical static timing analysis through learning spatial delay correlations
Statistical static timing analysis (SSTA) has been a popular research topic in recent years. A fundamental issue with applying SSTA in practice today is the lack of reliable and efficient statistical timing models (STM). Among many types of parameters required to be carefully modeled in an STM, spat...
Gespeichert in:
Hauptverfasser: | , , |
---|---|
Format: | Tagungsbericht |
Sprache: | eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | 154 |
---|---|
container_issue | |
container_start_page | 149 |
container_title | |
container_volume | |
creator | Lee, B.N. Wang, L.-C. Abadir, M.S. |
description | Statistical static timing analysis (SSTA) has been a popular research topic in recent years. A fundamental issue with applying SSTA in practice today is the lack of reliable and efficient statistical timing models (STM). Among many types of parameters required to be carefully modeled in an STM, spatial delay correlations are recognized as having significant impact on SSTA results. In this work, we assume that exact modeling of spatial delay correlations is quite difficult, and propose an experimental methodology to resolve this issue. The modeling accuracy requirement is relaxed by allowing SSTA to impose upper bounds and lower bounds on the delay correlations. These bounds can then be refined through learning the actual delay correlations from path delay testing on silicon. We utilize SSTA as the platform for learning and propose a Bayesian approach for learning spatial delay correlations. The effectiveness of the proposed methodology is illustrated through experiments on benchmark circuits |
doi_str_mv | 10.1109/DAC.2006.229198 |
format | Conference Proceeding |
fullrecord | <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_1688779</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>1688779</ieee_id><sourcerecordid>1688779</sourcerecordid><originalsourceid>FETCH-LOGICAL-i105t-ffda26c7818d45aa735ca62b041a409c7979a029684e6cb2150cd184df7bb3be3</originalsourceid><addsrcrecordid>eNotjEtLw0AURgdUsNauXbjJH0i8dybzWpb4hIIgKu7KzWTSjqRJyYyL_HsjdfUd-A6HsRuEAhHs3f26KjiAKji3aM0Zu0JppRXCoDpnC9DC5AjwdclWMX4DAKIwvJQL9vnm29D7JouJUogpOOpO7LIUDqHfZdRTN8UQs7Qfh5_dPus8jf3fE4-zN_uN72jK3DCOM6Qw9PGaXbTURb_63yX7eHx4r57zzevTS7Xe5AFBprxtG-LKaYOmKSWRFtKR4jWUSCVYp622BNwqU3rlao4SXIOmbFpd16L2YsluT93gvd8ex3CgcdqiMkZrK34B_DhSlw</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Refined statistical static timing analysis through learning spatial delay correlations</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Lee, B.N. ; Wang, L.-C. ; Abadir, M.S.</creator><creatorcontrib>Lee, B.N. ; Wang, L.-C. ; Abadir, M.S.</creatorcontrib><description>Statistical static timing analysis (SSTA) has been a popular research topic in recent years. A fundamental issue with applying SSTA in practice today is the lack of reliable and efficient statistical timing models (STM). Among many types of parameters required to be carefully modeled in an STM, spatial delay correlations are recognized as having significant impact on SSTA results. In this work, we assume that exact modeling of spatial delay correlations is quite difficult, and propose an experimental methodology to resolve this issue. The modeling accuracy requirement is relaxed by allowing SSTA to impose upper bounds and lower bounds on the delay correlations. These bounds can then be refined through learning the actual delay correlations from path delay testing on silicon. We utilize SSTA as the platform for learning and propose a Bayesian approach for learning spatial delay correlations. The effectiveness of the proposed methodology is illustrated through experiments on benchmark circuits</description><identifier>ISSN: 0738-100X</identifier><identifier>ISBN: 1595933816</identifier><identifier>ISBN: 9781595933812</identifier><identifier>DOI: 10.1109/DAC.2006.229198</identifier><language>eng</language><publisher>IEEE</publisher><subject>Algorithms ; Bayesian learning ; Bayesian methods ; Circuits ; delay correlations ; Delay effects ; Design ; Environmental economics ; Impedance ; Performance analysis ; Silicon ; Spatial resolution ; Statistical timing ; Testing ; Timing</subject><ispartof>2006 43rd ACM/IEEE Design Automation Conference, 2006, p.149-154</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/1688779$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,796,2057,4049,4050,27924,54757,54919</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/1688779$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Lee, B.N.</creatorcontrib><creatorcontrib>Wang, L.-C.</creatorcontrib><creatorcontrib>Abadir, M.S.</creatorcontrib><title>Refined statistical static timing analysis through learning spatial delay correlations</title><title>2006 43rd ACM/IEEE Design Automation Conference</title><addtitle>DAC</addtitle><description>Statistical static timing analysis (SSTA) has been a popular research topic in recent years. A fundamental issue with applying SSTA in practice today is the lack of reliable and efficient statistical timing models (STM). Among many types of parameters required to be carefully modeled in an STM, spatial delay correlations are recognized as having significant impact on SSTA results. In this work, we assume that exact modeling of spatial delay correlations is quite difficult, and propose an experimental methodology to resolve this issue. The modeling accuracy requirement is relaxed by allowing SSTA to impose upper bounds and lower bounds on the delay correlations. These bounds can then be refined through learning the actual delay correlations from path delay testing on silicon. We utilize SSTA as the platform for learning and propose a Bayesian approach for learning spatial delay correlations. The effectiveness of the proposed methodology is illustrated through experiments on benchmark circuits</description><subject>Algorithms</subject><subject>Bayesian learning</subject><subject>Bayesian methods</subject><subject>Circuits</subject><subject>delay correlations</subject><subject>Delay effects</subject><subject>Design</subject><subject>Environmental economics</subject><subject>Impedance</subject><subject>Performance analysis</subject><subject>Silicon</subject><subject>Spatial resolution</subject><subject>Statistical timing</subject><subject>Testing</subject><subject>Timing</subject><issn>0738-100X</issn><isbn>1595933816</isbn><isbn>9781595933812</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2006</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotjEtLw0AURgdUsNauXbjJH0i8dybzWpb4hIIgKu7KzWTSjqRJyYyL_HsjdfUd-A6HsRuEAhHs3f26KjiAKji3aM0Zu0JppRXCoDpnC9DC5AjwdclWMX4DAKIwvJQL9vnm29D7JouJUogpOOpO7LIUDqHfZdRTN8UQs7Qfh5_dPus8jf3fE4-zN_uN72jK3DCOM6Qw9PGaXbTURb_63yX7eHx4r57zzevTS7Xe5AFBprxtG-LKaYOmKSWRFtKR4jWUSCVYp622BNwqU3rlao4SXIOmbFpd16L2YsluT93gvd8ex3CgcdqiMkZrK34B_DhSlw</recordid><startdate>2006</startdate><enddate>2006</enddate><creator>Lee, B.N.</creator><creator>Wang, L.-C.</creator><creator>Abadir, M.S.</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>2006</creationdate><title>Refined statistical static timing analysis through learning spatial delay correlations</title><author>Lee, B.N. ; Wang, L.-C. ; Abadir, M.S.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i105t-ffda26c7818d45aa735ca62b041a409c7979a029684e6cb2150cd184df7bb3be3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2006</creationdate><topic>Algorithms</topic><topic>Bayesian learning</topic><topic>Bayesian methods</topic><topic>Circuits</topic><topic>delay correlations</topic><topic>Delay effects</topic><topic>Design</topic><topic>Environmental economics</topic><topic>Impedance</topic><topic>Performance analysis</topic><topic>Silicon</topic><topic>Spatial resolution</topic><topic>Statistical timing</topic><topic>Testing</topic><topic>Timing</topic><toplevel>online_resources</toplevel><creatorcontrib>Lee, B.N.</creatorcontrib><creatorcontrib>Wang, L.-C.</creatorcontrib><creatorcontrib>Abadir, M.S.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Lee, B.N.</au><au>Wang, L.-C.</au><au>Abadir, M.S.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Refined statistical static timing analysis through learning spatial delay correlations</atitle><btitle>2006 43rd ACM/IEEE Design Automation Conference</btitle><stitle>DAC</stitle><date>2006</date><risdate>2006</risdate><spage>149</spage><epage>154</epage><pages>149-154</pages><issn>0738-100X</issn><isbn>1595933816</isbn><isbn>9781595933812</isbn><abstract>Statistical static timing analysis (SSTA) has been a popular research topic in recent years. A fundamental issue with applying SSTA in practice today is the lack of reliable and efficient statistical timing models (STM). Among many types of parameters required to be carefully modeled in an STM, spatial delay correlations are recognized as having significant impact on SSTA results. In this work, we assume that exact modeling of spatial delay correlations is quite difficult, and propose an experimental methodology to resolve this issue. The modeling accuracy requirement is relaxed by allowing SSTA to impose upper bounds and lower bounds on the delay correlations. These bounds can then be refined through learning the actual delay correlations from path delay testing on silicon. We utilize SSTA as the platform for learning and propose a Bayesian approach for learning spatial delay correlations. The effectiveness of the proposed methodology is illustrated through experiments on benchmark circuits</abstract><pub>IEEE</pub><doi>10.1109/DAC.2006.229198</doi><tpages>6</tpages></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | ISSN: 0738-100X |
ispartof | 2006 43rd ACM/IEEE Design Automation Conference, 2006, p.149-154 |
issn | 0738-100X |
language | eng |
recordid | cdi_ieee_primary_1688779 |
source | IEEE Electronic Library (IEL) Conference Proceedings |
subjects | Algorithms Bayesian learning Bayesian methods Circuits delay correlations Delay effects Design Environmental economics Impedance Performance analysis Silicon Spatial resolution Statistical timing Testing Timing |
title | Refined statistical static timing analysis through learning spatial delay correlations |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-08T18%3A37%3A07IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Refined%20statistical%20static%20timing%20analysis%20through%20learning%20spatial%20delay%20correlations&rft.btitle=2006%2043rd%20ACM/IEEE%20Design%20Automation%20Conference&rft.au=Lee,%20B.N.&rft.date=2006&rft.spage=149&rft.epage=154&rft.pages=149-154&rft.issn=0738-100X&rft.isbn=1595933816&rft.isbn_list=9781595933812&rft_id=info:doi/10.1109/DAC.2006.229198&rft_dat=%3Cieee_6IE%3E1688779%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=1688779&rfr_iscdi=true |