Error Correction in High-Speed Arithmetic

In high-speed multipliers, multiplication is activated by processing a group of bits in parallel. As a result, any defects in circuitry produce possible errors in positions that are separated by fixed periods. A class of codes for the correction of such iterative error patterns resulting from a sing...

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Veröffentlicht in:	IEEE transactions on computers 1972-05, Vol.C-21 (5), p.433-438
Hauptverfasser:	Chien, R.T., Se June Hong
Format:	Artikel
Sprache:	eng
Schlagworte:	Arithmetic codes computer reliability error correction in high-speed computation error detection and correction fault tolerant computing
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