Pipelined Block-Serial Decoder Architecture for Structured Ldpc Codes

We present a pipelined block-serial decoder architecture for structured LDPC codes, implementing the layered-mode belief-propagation. We introduce the concept of LLR-update and mirror memory to enforce a pipelined decoding schedule. The pipelined architecture improves the latency of the LDPC decoder...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Bhatt, T., Sundaramurthy, V., Stolpman, V., McCain, D.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Code standards Delay Forward error correction Hardware Iterative decoding Mirrors Parity check codes Performance loss Throughput USA Councils
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