Pipelined Block-Serial Decoder Architecture for Structured Ldpc Codes
We present a pipelined block-serial decoder architecture for structured LDPC codes, implementing the layered-mode belief-propagation. We introduce the concept of LLR-update and mirror memory to enforce a pipelined decoding schedule. The pipelined architecture improves the latency of the LDPC decoder...
Gespeichert in:
| Hauptverfasser: | , , , |
|---|---|
| Format: | Tagungsbericht |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | IV |
|---|---|
| container_issue | |
| container_start_page | IV |
| container_title | |
| container_volume | 4 |
| creator | Bhatt, T. Sundaramurthy, V. Stolpman, V. McCain, D. |
| description | We present a pipelined block-serial decoder architecture for structured LDPC codes, implementing the layered-mode belief-propagation. We introduce the concept of LLR-update and mirror memory to enforce a pipelined decoding schedule. The pipelined architecture improves the latency of the LDPC decoder by about 2x-3x and has negligible performance loss when implemented with clever layer scheduling. We also present a low-complexity check-node architecture suitable for block-serial processing and utilize the properties of the min approximation to significantly reduce the memory requirement. The proposed architecture is suitable for mobile devices with data-rates of tens of mbps |
| doi_str_mv | 10.1109/ICASSP.2006.1660946 |
| format | Conference Proceeding |
| fullrecord | <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_1660946</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>1660946</ieee_id><sourcerecordid>1660946</sourcerecordid><originalsourceid>FETCH-ieee_primary_16609463</originalsourceid><addsrcrecordid>eNp9jrGOgkAURV9cTSTKF9DMD8C-N4yDU7qsRhMLEyzsDBkecRQXMmDh3-9mY211c3JOcQEiwoQIzecuXxXFIZGIOiGt0Sg9gkCmmYnJ4OkDQpMtSUmlUGmzHENAC4mxJmWmEPb9FRHJ6EylMoD1wXXcuB-uxFfT2ltcsHdlI77ZthV7sfL24ga2w8OzqFsvisE__qkS-6qzIv_L-jlM6rLpOXztDKLN-phvY8fM5867e-mf59fZ9L39BUOlP2s</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Pipelined Block-Serial Decoder Architecture for Structured Ldpc Codes</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Bhatt, T. ; Sundaramurthy, V. ; Stolpman, V. ; McCain, D.</creator><creatorcontrib>Bhatt, T. ; Sundaramurthy, V. ; Stolpman, V. ; McCain, D.</creatorcontrib><description>We present a pipelined block-serial decoder architecture for structured LDPC codes, implementing the layered-mode belief-propagation. We introduce the concept of LLR-update and mirror memory to enforce a pipelined decoding schedule. The pipelined architecture improves the latency of the LDPC decoder by about 2x-3x and has negligible performance loss when implemented with clever layer scheduling. We also present a low-complexity check-node architecture suitable for block-serial processing and utilize the properties of the min approximation to significantly reduce the memory requirement. The proposed architecture is suitable for mobile devices with data-rates of tens of mbps</description><identifier>ISSN: 1520-6149</identifier><identifier>ISBN: 9781424404698</identifier><identifier>ISBN: 142440469X</identifier><identifier>EISSN: 2379-190X</identifier><identifier>DOI: 10.1109/ICASSP.2006.1660946</identifier><language>eng</language><publisher>IEEE</publisher><subject>Code standards ; Delay ; Forward error correction ; Hardware ; Iterative decoding ; Mirrors ; Parity check codes ; Performance loss ; Throughput ; USA Councils</subject><ispartof>2006 IEEE International Conference on Acoustics Speech and Signal Processing Proceedings, 2006, Vol.4, p.IV-IV</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/1660946$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2058,4050,4051,27925,54920</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/1660946$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Bhatt, T.</creatorcontrib><creatorcontrib>Sundaramurthy, V.</creatorcontrib><creatorcontrib>Stolpman, V.</creatorcontrib><creatorcontrib>McCain, D.</creatorcontrib><title>Pipelined Block-Serial Decoder Architecture for Structured Ldpc Codes</title><title>2006 IEEE International Conference on Acoustics Speech and Signal Processing Proceedings</title><addtitle>ICASSP</addtitle><description>We present a pipelined block-serial decoder architecture for structured LDPC codes, implementing the layered-mode belief-propagation. We introduce the concept of LLR-update and mirror memory to enforce a pipelined decoding schedule. The pipelined architecture improves the latency of the LDPC decoder by about 2x-3x and has negligible performance loss when implemented with clever layer scheduling. We also present a low-complexity check-node architecture suitable for block-serial processing and utilize the properties of the min approximation to significantly reduce the memory requirement. The proposed architecture is suitable for mobile devices with data-rates of tens of mbps</description><subject>Code standards</subject><subject>Delay</subject><subject>Forward error correction</subject><subject>Hardware</subject><subject>Iterative decoding</subject><subject>Mirrors</subject><subject>Parity check codes</subject><subject>Performance loss</subject><subject>Throughput</subject><subject>USA Councils</subject><issn>1520-6149</issn><issn>2379-190X</issn><isbn>9781424404698</isbn><isbn>142440469X</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2006</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNp9jrGOgkAURV9cTSTKF9DMD8C-N4yDU7qsRhMLEyzsDBkecRQXMmDh3-9mY211c3JOcQEiwoQIzecuXxXFIZGIOiGt0Sg9gkCmmYnJ4OkDQpMtSUmlUGmzHENAC4mxJmWmEPb9FRHJ6EylMoD1wXXcuB-uxFfT2ltcsHdlI77ZthV7sfL24ga2w8OzqFsvisE__qkS-6qzIv_L-jlM6rLpOXztDKLN-phvY8fM5867e-mf59fZ9L39BUOlP2s</recordid><startdate>2006</startdate><enddate>2006</enddate><creator>Bhatt, T.</creator><creator>Sundaramurthy, V.</creator><creator>Stolpman, V.</creator><creator>McCain, D.</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>2006</creationdate><title>Pipelined Block-Serial Decoder Architecture for Structured Ldpc Codes</title><author>Bhatt, T. ; Sundaramurthy, V. ; Stolpman, V. ; McCain, D.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-ieee_primary_16609463</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2006</creationdate><topic>Code standards</topic><topic>Delay</topic><topic>Forward error correction</topic><topic>Hardware</topic><topic>Iterative decoding</topic><topic>Mirrors</topic><topic>Parity check codes</topic><topic>Performance loss</topic><topic>Throughput</topic><topic>USA Councils</topic><toplevel>online_resources</toplevel><creatorcontrib>Bhatt, T.</creatorcontrib><creatorcontrib>Sundaramurthy, V.</creatorcontrib><creatorcontrib>Stolpman, V.</creatorcontrib><creatorcontrib>McCain, D.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Bhatt, T.</au><au>Sundaramurthy, V.</au><au>Stolpman, V.</au><au>McCain, D.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Pipelined Block-Serial Decoder Architecture for Structured Ldpc Codes</atitle><btitle>2006 IEEE International Conference on Acoustics Speech and Signal Processing Proceedings</btitle><stitle>ICASSP</stitle><date>2006</date><risdate>2006</risdate><volume>4</volume><spage>IV</spage><epage>IV</epage><pages>IV-IV</pages><issn>1520-6149</issn><eissn>2379-190X</eissn><isbn>9781424404698</isbn><isbn>142440469X</isbn><abstract>We present a pipelined block-serial decoder architecture for structured LDPC codes, implementing the layered-mode belief-propagation. We introduce the concept of LLR-update and mirror memory to enforce a pipelined decoding schedule. The pipelined architecture improves the latency of the LDPC decoder by about 2x-3x and has negligible performance loss when implemented with clever layer scheduling. We also present a low-complexity check-node architecture suitable for block-serial processing and utilize the properties of the min approximation to significantly reduce the memory requirement. The proposed architecture is suitable for mobile devices with data-rates of tens of mbps</abstract><pub>IEEE</pub><doi>10.1109/ICASSP.2006.1660946</doi></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 1520-6149 |
| ispartof | 2006 IEEE International Conference on Acoustics Speech and Signal Processing Proceedings, 2006, Vol.4, p.IV-IV |
| issn | 1520-6149 2379-190X |
| language | eng |
| recordid | cdi_ieee_primary_1660946 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Code standards Delay Forward error correction Hardware Iterative decoding Mirrors Parity check codes Performance loss Throughput USA Councils |
| title | Pipelined Block-Serial Decoder Architecture for Structured Ldpc Codes |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-03T06%3A16%3A14IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Pipelined%20Block-Serial%20Decoder%20Architecture%20for%20Structured%20Ldpc%20Codes&rft.btitle=2006%20IEEE%20International%20Conference%20on%20Acoustics%20Speech%20and%20Signal%20Processing%20Proceedings&rft.au=Bhatt,%20T.&rft.date=2006&rft.volume=4&rft.spage=IV&rft.epage=IV&rft.pages=IV-IV&rft.issn=1520-6149&rft.eissn=2379-190X&rft.isbn=9781424404698&rft.isbn_list=142440469X&rft_id=info:doi/10.1109/ICASSP.2006.1660946&rft_dat=%3Cieee_6IE%3E1660946%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=1660946&rfr_iscdi=true |