STAX: Statistical Crosstalk Target Set Compaction
This paper presents STAX, a crosstalk target set compaction framework to reduce the complexity of the crosstalk ATPG process by pruning non-fault-producing targets. In general, existing pruning techniques do not employ their processes in a cost-effective manner. Neither do they handle process variat...
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creator | Shahin Nazarian Massoud Pedram Gupta, S.K. Breuer, M.A. |
description | This paper presents STAX, a crosstalk target set compaction framework to reduce the complexity of the crosstalk ATPG process by pruning non-fault-producing targets. In general, existing pruning techniques do not employ their processes in a cost-effective manner. Neither do they handle process variations properly. To address the first weakness, this paper presents a framework to determine a sequence of available analysis and pruning tool invocations to prune as many of the crosstalk targets as fast as possible. As a result, an initially enormous collection of crosstalk targets is usually reduced to a very small set of targets via a vectorless process. A statistical static timing analyzer is developed and embedded to address the second shortcoming of existing approaches. Experimental results on ISCAS'85 benchmark demonstrate that STAX greatly improves the runtime compared to other crosstalk target pruning methodologies, including ATPG, with no prior target set compaction |
doi_str_mv | 10.1109/DATE.2006.243844 |
format | Conference Proceeding |
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Experimental results on ISCAS'85 benchmark demonstrate that STAX greatly improves the runtime compared to other crosstalk target pruning methodologies, including ATPG, with no prior target set compaction</description><subject>ATPG</subject><subject>Automatic test pattern generation</subject><subject>Circuit faults</subject><subject>Circuit noise</subject><subject>Circuit testing</subject><subject>Compaction</subject><subject>compaction degree</subject><subject>Coupling circuits</subject><subject>Crosstalk</subject><subject>fault-producing target</subject><subject>Integrated circuit interconnections</subject><subject>pruning power</subject><subject>safe target</subject><subject>statistical static timing analyzer</subject><subject>Timing</subject><subject>Very large scale integration</subject><issn>1530-1591</issn><issn>1558-1101</issn><isbn>3981080114</isbn><isbn>9783981080117</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2006</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotzMtKxDAYBeDgBRzH2Qtu-gKp-XOPu1LHCwy4aAV3Q5qLRDt2aLLx7a3ogcNZfHAQugZSAxBze9_025oSImvKmeb8BK1ACI0XhFN0yYwGogkAP_sFRjAIAxdok_MHWcIMB6lXCLq-eburumJLyiU5O1btPOVc7PhZ9XZ-D6XqlrbT4WhdSdPXFTqPdsxh879r9Pqw7dsnvHt5fG6bHU7AKMdOQmCWioGHQSuvgmdOAXVqABq18M4EFR0PgloXiZRSEFDeU-WFgiEatkY3f78phLA_zulg5-89yIUZZz8sQ0Ue</recordid><startdate>2006</startdate><enddate>2006</enddate><creator>Shahin Nazarian</creator><creator>Massoud Pedram</creator><creator>Gupta, S.K.</creator><creator>Breuer, M.A.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>2006</creationdate><title>STAX: Statistical Crosstalk Target Set Compaction</title><author>Shahin Nazarian ; Massoud Pedram ; Gupta, S.K. ; Breuer, M.A.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i1324-c61e3a25b4eb87d7ed3c712c7b12f85dc9e7fc4e52acf06665017dd27d571bf93</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2006</creationdate><topic>ATPG</topic><topic>Automatic test pattern generation</topic><topic>Circuit faults</topic><topic>Circuit noise</topic><topic>Circuit testing</topic><topic>Compaction</topic><topic>compaction degree</topic><topic>Coupling circuits</topic><topic>Crosstalk</topic><topic>fault-producing target</topic><topic>Integrated circuit interconnections</topic><topic>pruning power</topic><topic>safe target</topic><topic>statistical static timing analyzer</topic><topic>Timing</topic><topic>Very large scale integration</topic><toplevel>online_resources</toplevel><creatorcontrib>Shahin Nazarian</creatorcontrib><creatorcontrib>Massoud Pedram</creatorcontrib><creatorcontrib>Gupta, S.K.</creatorcontrib><creatorcontrib>Breuer, M.A.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Shahin Nazarian</au><au>Massoud Pedram</au><au>Gupta, S.K.</au><au>Breuer, M.A.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>STAX: Statistical Crosstalk Target Set Compaction</atitle><btitle>Proceedings of the Design Automation & Test in Europe Conference</btitle><stitle>DATE</stitle><date>2006</date><risdate>2006</risdate><volume>2</volume><spage>1</spage><epage>6</epage><pages>1-6</pages><issn>1530-1591</issn><eissn>1558-1101</eissn><isbn>3981080114</isbn><isbn>9783981080117</isbn><abstract>This paper presents STAX, a crosstalk target set compaction framework to reduce the complexity of the crosstalk ATPG process by pruning non-fault-producing targets. In general, existing pruning techniques do not employ their processes in a cost-effective manner. Neither do they handle process variations properly. To address the first weakness, this paper presents a framework to determine a sequence of available analysis and pruning tool invocations to prune as many of the crosstalk targets as fast as possible. As a result, an initially enormous collection of crosstalk targets is usually reduced to a very small set of targets via a vectorless process. A statistical static timing analyzer is developed and embedded to address the second shortcoming of existing approaches. Experimental results on ISCAS'85 benchmark demonstrate that STAX greatly improves the runtime compared to other crosstalk target pruning methodologies, including ATPG, with no prior target set compaction</abstract><pub>IEEE</pub><doi>10.1109/DATE.2006.243844</doi><tpages>6</tpages><oa>free_for_read</oa></addata></record> |
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issn | 1530-1591 1558-1101 |
language | eng |
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source | IEEE Electronic Library (IEL) Conference Proceedings |
subjects | ATPG Automatic test pattern generation Circuit faults Circuit noise Circuit testing Compaction compaction degree Coupling circuits Crosstalk fault-producing target Integrated circuit interconnections pruning power safe target statistical static timing analyzer Timing Very large scale integration |
title | STAX: Statistical Crosstalk Target Set Compaction |
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