Reducing the Sub-threshold and Gate-tunneling Leakage of SRAM Cells using Dual-Vt and Dual-Tox Assignment

Aggressive CMOS scaling results in low threshold voltage and thin oxide thickness for transistors manufactured in very deep submicron regime. As a result, reducing the subthreshold and gate-tunneling leakage currents has become one of the most important criteria in the design of VLSI circuits. This...

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Bibliographische Detailangaben

Hauptverfasser:	Amelifard, B., Fallah, F., Pedram, M.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Circuits Decoding Delay Leakage current Manufacturing Power dissipation Random access memory Read-write memory Threshold voltage Very large scale integration
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