A reconfigurable HW/SW platform for computation intensive high-resolution real-time digital film applications
This paper presents a multi-board, multi-FPGA hardware/software architecture, for computation intensive, high resolution (2048times2048pixels), real-time (24 frames per second) digital film processing. It is based on Xilinx Virtex-II Pro FPGAs, large SDRAM memories for multiple frame storage and a P...
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| creator | do Carmo Lucas, A. Heithecker, S. Riiffer, P. Ernst, R. Ruckert, H. Wischermann, G. Gebel, K. Fach, R. Huther, W. Eichner, S. Scheller, G. |
| description | This paper presents a multi-board, multi-FPGA hardware/software architecture, for computation intensive, high resolution (2048times2048pixels), real-time (24 frames per second) digital film processing. It is based on Xilinx Virtex-II Pro FPGAs, large SDRAM memories for multiple frame storage and a PCI express communication network. The architecture reaches record performance running a complex noise reduction algorithm including a 2.5 dimensions DWT and a full 16times16 motion estimation at 24 fps requiring a total of 203 Gops/s net computing performance and a total of 28 Gbit/s DDR-SDRAM frame memory bandwidth. To increase design productivity and yet achieve high clock rates (125MHz), the architecture combines macro component configuration and macro level floorplanning with weak programmability using distributed microcoding. As an example, the core of the bidirectional motion estimation using 2772 CLBs reaching 155 Gop/s (1538 op/pixel) requiring 7 Gbit/s external memory bandwidth was developed in two men-months |
| doi_str_mv | 10.1109/DATE.2006.244085 |
| format | Conference Proceeding |
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It is based on Xilinx Virtex-II Pro FPGAs, large SDRAM memories for multiple frame storage and a PCI express communication network. The architecture reaches record performance running a complex noise reduction algorithm including a 2.5 dimensions DWT and a full 16times16 motion estimation at 24 fps requiring a total of 203 Gops/s net computing performance and a total of 28 Gbit/s DDR-SDRAM frame memory bandwidth. To increase design productivity and yet achieve high clock rates (125MHz), the architecture combines macro component configuration and macro level floorplanning with weak programmability using distributed microcoding. As an example, the core of the bidirectional motion estimation using 2772 CLBs reaching 155 Gop/s (1538 op/pixel) requiring 7 Gbit/s external memory bandwidth was developed in two men-months</abstract><pub>IEEE</pub><doi>10.1109/DATE.2006.244085</doi><tpages>6</tpages></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 1530-1591 |
| ispartof | Proceedings of the Design Automation & Test in Europe Conference, 2006, Vol.1, p.1-6 |
| issn | 1530-1591 1558-1101 |
| language | eng |
| recordid | cdi_ieee_primary_1656875 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Application software Bandwidth Communication networks Computer architecture digital film Field programmable gate arrays FPGA Hardware Motion estimation Noise reduction reconfigurable SDRAM Software architecture stream-based architechture weak-programming |
| title | A reconfigurable HW/SW platform for computation intensive high-resolution real-time digital film applications |
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