Thermal Development, Modeling and Characterization of the Cell Processor Module
Optimal package thermal design for today's high power processors is critical to meet demanding performance, cost, and reliability objectives. This paper describes the thermal characterization and development of the first generation CELL processor, developed jointly by Sony, Toshiba and IBM. The...
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creator | Wakil, J. Questad, D. Gaynes, M. Hamann, H. Weger, A. Wang, M. Harvey, P. Yarmchuk, E. Coffin, J. Yazawa, K. Tamura, T. Takiguchi, I. |
description | Optimal package thermal design for today's high power processors is critical to meet demanding performance, cost, and reliability objectives. This paper describes the thermal characterization and development of the first generation CELL processor, developed jointly by Sony, Toshiba and IBM. The package not only provides the very high bandwidth necessary for electrical performance, but also achieves low thermal resistance to dissipate high power and maintain low die temperatures with superior reliability. The focus of the paper is the first level package. The target thermal resistance for the package is explained as determined from detailed 2nd level modeling and novel power map calculation and validation techniques are discussed. Thermal and mechanical modeling are used characterize the effects of the thermal interface material (TIM) on the thermal performance and mechanical response of the package. The thermal test strategy and the TIM characterization techniques are described. In summary, the paper describes the novel thermal modeling and characterization methodology used in the design process, allowing high heat flux in a low cost system application |
doi_str_mv | 10.1109/ITHERM.2006.1645355 |
format | Conference Proceeding |
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This paper describes the thermal characterization and development of the first generation CELL processor, developed jointly by Sony, Toshiba and IBM. The package not only provides the very high bandwidth necessary for electrical performance, but also achieves low thermal resistance to dissipate high power and maintain low die temperatures with superior reliability. The focus of the paper is the first level package. The target thermal resistance for the package is explained as determined from detailed 2nd level modeling and novel power map calculation and validation techniques are discussed. Thermal and mechanical modeling are used characterize the effects of the thermal interface material (TIM) on the thermal performance and mechanical response of the package. The thermal test strategy and the TIM characterization techniques are described. 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The thermal test strategy and the TIM characterization techniques are described. In summary, the paper describes the novel thermal modeling and characterization methodology used in the design process, allowing high heat flux in a low cost system application</description><subject>Bandwidth</subject><subject>Character generation</subject><subject>Cost function</subject><subject>Electric resistance</subject><subject>Maintenance</subject><subject>Packaging</subject><subject>Process design</subject><subject>Temperature</subject><subject>Testing</subject><subject>Thermal resistance</subject><issn>1087-9870</issn><issn>2577-0799</issn><isbn>0780395247</isbn><isbn>9780780395244</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2006</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotkMtOwzAQRS0eEqH0C7rxB5Ay48R2vESh0EqtilD2lRNPSJCTVE5Agq-niK7u6hwdXcYWCEtEMA-bYr162y0FgFqiSmUi5QWLhNQ6Bm3MJbsFnUFipEj1FYsQMh2bTMMNm4_jBwCgUQaViti-aCh01vMn-iI_HDvqp3u-Gxz5tn_ntnc8b2yw1USh_bFTO_R8qPnUEM_Je_4ahorGcQh_zKenO3ZdWz_S_LwzVjyvinwdb_cvm_xxG7cGptjVqaqEcKpyKenylIynHjSlStFJIKysQFHKrEzAZSBRYVq7SiUahEUFyYwt_rUtER2Ooe1s-D6cr0h-AXc8UEw</recordid><startdate>2006</startdate><enddate>2006</enddate><creator>Wakil, J.</creator><creator>Questad, D.</creator><creator>Gaynes, M.</creator><creator>Hamann, H.</creator><creator>Weger, A.</creator><creator>Wang, M.</creator><creator>Harvey, P.</creator><creator>Yarmchuk, E.</creator><creator>Coffin, J.</creator><creator>Yazawa, K.</creator><creator>Tamura, T.</creator><creator>Takiguchi, I.</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>2006</creationdate><title>Thermal Development, Modeling and Characterization of the Cell Processor Module</title><author>Wakil, J. ; Questad, D. ; Gaynes, M. ; Hamann, H. ; Weger, A. ; Wang, M. ; Harvey, P. ; Yarmchuk, E. ; Coffin, J. ; Yazawa, K. ; Tamura, T. ; Takiguchi, I.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i90t-df46c22d6cd4e7b799169119b641d50e1ca212b58b30d8051614fdc63702a1603</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2006</creationdate><topic>Bandwidth</topic><topic>Character generation</topic><topic>Cost function</topic><topic>Electric resistance</topic><topic>Maintenance</topic><topic>Packaging</topic><topic>Process design</topic><topic>Temperature</topic><topic>Testing</topic><topic>Thermal resistance</topic><toplevel>online_resources</toplevel><creatorcontrib>Wakil, J.</creatorcontrib><creatorcontrib>Questad, D.</creatorcontrib><creatorcontrib>Gaynes, M.</creatorcontrib><creatorcontrib>Hamann, H.</creatorcontrib><creatorcontrib>Weger, A.</creatorcontrib><creatorcontrib>Wang, M.</creatorcontrib><creatorcontrib>Harvey, P.</creatorcontrib><creatorcontrib>Yarmchuk, E.</creatorcontrib><creatorcontrib>Coffin, J.</creatorcontrib><creatorcontrib>Yazawa, K.</creatorcontrib><creatorcontrib>Tamura, T.</creatorcontrib><creatorcontrib>Takiguchi, I.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Wakil, J.</au><au>Questad, D.</au><au>Gaynes, M.</au><au>Hamann, H.</au><au>Weger, A.</au><au>Wang, M.</au><au>Harvey, P.</au><au>Yarmchuk, E.</au><au>Coffin, J.</au><au>Yazawa, K.</au><au>Tamura, T.</au><au>Takiguchi, I.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Thermal Development, Modeling and Characterization of the Cell Processor Module</atitle><btitle>Thermal and Thermomechanical Proceedings 10th Intersociety Conference on Phenomena in Electronics Systems, 2006. ITHERM 2006</btitle><stitle>ITHERM</stitle><date>2006</date><risdate>2006</risdate><spage>289</spage><epage>296</epage><pages>289-296</pages><issn>1087-9870</issn><eissn>2577-0799</eissn><isbn>0780395247</isbn><isbn>9780780395244</isbn><abstract>Optimal package thermal design for today's high power processors is critical to meet demanding performance, cost, and reliability objectives. This paper describes the thermal characterization and development of the first generation CELL processor, developed jointly by Sony, Toshiba and IBM. The package not only provides the very high bandwidth necessary for electrical performance, but also achieves low thermal resistance to dissipate high power and maintain low die temperatures with superior reliability. The focus of the paper is the first level package. The target thermal resistance for the package is explained as determined from detailed 2nd level modeling and novel power map calculation and validation techniques are discussed. Thermal and mechanical modeling are used characterize the effects of the thermal interface material (TIM) on the thermal performance and mechanical response of the package. The thermal test strategy and the TIM characterization techniques are described. In summary, the paper describes the novel thermal modeling and characterization methodology used in the design process, allowing high heat flux in a low cost system application</abstract><pub>IEEE</pub><doi>10.1109/ITHERM.2006.1645355</doi><tpages>8</tpages></addata></record> |
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ispartof | Thermal and Thermomechanical Proceedings 10th Intersociety Conference on Phenomena in Electronics Systems, 2006. ITHERM 2006, 2006, p.289-296 |
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language | eng |
recordid | cdi_ieee_primary_1645355 |
source | IEEE Electronic Library (IEL) Conference Proceedings |
subjects | Bandwidth Character generation Cost function Electric resistance Maintenance Packaging Process design Temperature Testing Thermal resistance |
title | Thermal Development, Modeling and Characterization of the Cell Processor Module |
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