Impact of failure criteria on the reliability prediction of CMOS devices with ultrathin gate oxides based on voltage ramp stress
The gate oxide reliability prediction based on the soft breakdown (SBD) failure criteria limits the operation voltage of future CMOS technologies. Progressive wear-out observed in ultrathin gate oxides leads to a delayed hard dielectric breakdown and can therefore effectively increase the reliabilit...
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Veröffentlicht in: | IEEE electron device letters 2006-07, Vol.27 (7), p.609-611 |
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creator | Kerber, A. Pompl, T. Rohner, M. Mosig, K. Kerber, M. |
description | The gate oxide reliability prediction based on the soft breakdown (SBD) failure criteria limits the operation voltage of future CMOS technologies. Progressive wear-out observed in ultrathin gate oxides leads to a delayed hard dielectric breakdown and can therefore effectively increase the reliability margin. For quantification of this effect, voltage ramp tests were applied to a large sample size and the results linked to constant voltage stress. Based on area scaling, it will be shown that a significant improvement for n- and p-FET devices is obtained when considering the area independent, uncorrelated progressive wear-out of a localized SBD spot. |
doi_str_mv | 10.1109/LED.2006.877710 |
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fullrecord | <record><control><sourceid>proquest_RIE</sourceid><recordid>TN_cdi_ieee_primary_1644842</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>1644842</ieee_id><sourcerecordid>2543769461</sourcerecordid><originalsourceid>FETCH-LOGICAL-c350t-f32e57fe163cc8e648b34b78216294fd66915c24f52179724d915c6d3b3270863</originalsourceid><addsrcrecordid>eNpdkUFv1DAQhS0EEkvhzIGLhYQ4ZeuxHTs5om0plRb1AJwjxxl3XXmTYDuF3vjpdbSVKnEajd733oz0CHkPbAvA2vP95cWWM6a2jdYa2AuygbpuKlYr8ZJsmJZQCWDqNXmT0h1jIKWWG_Lv-jgbm-nkqDM-LBGpjT5j9IZOI80HpBGDN70PPj_QOeLgbfZFKo7d95sfdMB7bzHRPz4f6BJyNPngR3prMtLprx-K1JuEwxp3P4VsbkukOc405YgpvSWvnAkJ3z3NM_Lr6-XP3bdqf3N1vfuyr6yoWa6c4Fhrh6CEtQ0q2fRC9rrhoHgr3aBUC7Xl0tUcdKu5HNZdDaIXXLNGiTPy-ZQ7x-n3gil3R58shmBGnJbUtSCVVCB4IT_-R95NSxzLcwXiACChKdD5CbJxSimi6-bojyY-dMC6tY-u9NGtfXSnPorj01OsSdYEF81ofXq26VZCzdbzH06cR8RnWUnZSC4eAdJFkt8</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>912111418</pqid></control><display><type>article</type><title>Impact of failure criteria on the reliability prediction of CMOS devices with ultrathin gate oxides based on voltage ramp stress</title><source>IEEE Electronic Library (IEL)</source><creator>Kerber, A. ; Pompl, T. ; Rohner, M. ; Mosig, K. ; Kerber, M.</creator><creatorcontrib>Kerber, A. ; Pompl, T. ; Rohner, M. ; Mosig, K. ; Kerber, M.</creatorcontrib><description>The gate oxide reliability prediction based on the soft breakdown (SBD) failure criteria limits the operation voltage of future CMOS technologies. Progressive wear-out observed in ultrathin gate oxides leads to a delayed hard dielectric breakdown and can therefore effectively increase the reliability margin. For quantification of this effect, voltage ramp tests were applied to a large sample size and the results linked to constant voltage stress. Based on area scaling, it will be shown that a significant improvement for n- and p-FET devices is obtained when considering the area independent, uncorrelated progressive wear-out of a localized SBD spot.</description><identifier>ISSN: 0741-3106</identifier><identifier>EISSN: 1558-0563</identifier><identifier>DOI: 10.1109/LED.2006.877710</identifier><identifier>CODEN: EDLEDZ</identifier><language>eng</language><publisher>New York, NY: IEEE</publisher><subject>Acceleration ; Applied sciences ; Breakdown voltage ; CMOS ; CMOS technology ; Compound structure devices ; Condition monitoring ; Criteria ; Delay effects ; Design. Technologies. Operation analysis. Testing ; Devices ; Dielectric breakdown ; Electric breakdown ; Electric potential ; Electronics ; Exact sciences and technology ; Gates ; Integrated circuits ; Lead compounds ; MOS devices ; Oxides ; Ramps ; reliability ; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices ; Stress ; Testing ; Transistors ; Voltage</subject><ispartof>IEEE electron device letters, 2006-07, Vol.27 (7), p.609-611</ispartof><rights>2006 INIST-CNRS</rights><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2006</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c350t-f32e57fe163cc8e648b34b78216294fd66915c24f52179724d915c6d3b3270863</citedby><cites>FETCH-LOGICAL-c350t-f32e57fe163cc8e648b34b78216294fd66915c24f52179724d915c6d3b3270863</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/1644842$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,796,27924,27925,54758</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/1644842$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=17941502$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><creatorcontrib>Kerber, A.</creatorcontrib><creatorcontrib>Pompl, T.</creatorcontrib><creatorcontrib>Rohner, M.</creatorcontrib><creatorcontrib>Mosig, K.</creatorcontrib><creatorcontrib>Kerber, M.</creatorcontrib><title>Impact of failure criteria on the reliability prediction of CMOS devices with ultrathin gate oxides based on voltage ramp stress</title><title>IEEE electron device letters</title><addtitle>LED</addtitle><description>The gate oxide reliability prediction based on the soft breakdown (SBD) failure criteria limits the operation voltage of future CMOS technologies. Progressive wear-out observed in ultrathin gate oxides leads to a delayed hard dielectric breakdown and can therefore effectively increase the reliability margin. For quantification of this effect, voltage ramp tests were applied to a large sample size and the results linked to constant voltage stress. Based on area scaling, it will be shown that a significant improvement for n- and p-FET devices is obtained when considering the area independent, uncorrelated progressive wear-out of a localized SBD spot.</description><subject>Acceleration</subject><subject>Applied sciences</subject><subject>Breakdown voltage</subject><subject>CMOS</subject><subject>CMOS technology</subject><subject>Compound structure devices</subject><subject>Condition monitoring</subject><subject>Criteria</subject><subject>Delay effects</subject><subject>Design. Technologies. Operation analysis. Testing</subject><subject>Devices</subject><subject>Dielectric breakdown</subject><subject>Electric breakdown</subject><subject>Electric potential</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>Gates</subject><subject>Integrated circuits</subject><subject>Lead compounds</subject><subject>MOS devices</subject><subject>Oxides</subject><subject>Ramps</subject><subject>reliability</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><subject>Stress</subject><subject>Testing</subject><subject>Transistors</subject><subject>Voltage</subject><issn>0741-3106</issn><issn>1558-0563</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2006</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNpdkUFv1DAQhS0EEkvhzIGLhYQ4ZeuxHTs5om0plRb1AJwjxxl3XXmTYDuF3vjpdbSVKnEajd733oz0CHkPbAvA2vP95cWWM6a2jdYa2AuygbpuKlYr8ZJsmJZQCWDqNXmT0h1jIKWWG_Lv-jgbm-nkqDM-LBGpjT5j9IZOI80HpBGDN70PPj_QOeLgbfZFKo7d95sfdMB7bzHRPz4f6BJyNPngR3prMtLprx-K1JuEwxp3P4VsbkukOc405YgpvSWvnAkJ3z3NM_Lr6-XP3bdqf3N1vfuyr6yoWa6c4Fhrh6CEtQ0q2fRC9rrhoHgr3aBUC7Xl0tUcdKu5HNZdDaIXXLNGiTPy-ZQ7x-n3gil3R58shmBGnJbUtSCVVCB4IT_-R95NSxzLcwXiACChKdD5CbJxSimi6-bojyY-dMC6tY-u9NGtfXSnPorj01OsSdYEF81ofXq26VZCzdbzH06cR8RnWUnZSC4eAdJFkt8</recordid><startdate>20060701</startdate><enddate>20060701</enddate><creator>Kerber, A.</creator><creator>Pompl, T.</creator><creator>Rohner, M.</creator><creator>Mosig, K.</creator><creator>Kerber, M.</creator><general>IEEE</general><general>Institute of Electrical and Electronics Engineers</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>IQODW</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><scope>F28</scope><scope>FR3</scope></search><sort><creationdate>20060701</creationdate><title>Impact of failure criteria on the reliability prediction of CMOS devices with ultrathin gate oxides based on voltage ramp stress</title><author>Kerber, A. ; Pompl, T. ; Rohner, M. ; Mosig, K. ; Kerber, M.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c350t-f32e57fe163cc8e648b34b78216294fd66915c24f52179724d915c6d3b3270863</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2006</creationdate><topic>Acceleration</topic><topic>Applied sciences</topic><topic>Breakdown voltage</topic><topic>CMOS</topic><topic>CMOS technology</topic><topic>Compound structure devices</topic><topic>Condition monitoring</topic><topic>Criteria</topic><topic>Delay effects</topic><topic>Design. Technologies. Operation analysis. Testing</topic><topic>Devices</topic><topic>Dielectric breakdown</topic><topic>Electric breakdown</topic><topic>Electric potential</topic><topic>Electronics</topic><topic>Exact sciences and technology</topic><topic>Gates</topic><topic>Integrated circuits</topic><topic>Lead compounds</topic><topic>MOS devices</topic><topic>Oxides</topic><topic>Ramps</topic><topic>reliability</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</topic><topic>Stress</topic><topic>Testing</topic><topic>Transistors</topic><topic>Voltage</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Kerber, A.</creatorcontrib><creatorcontrib>Pompl, T.</creatorcontrib><creatorcontrib>Rohner, M.</creatorcontrib><creatorcontrib>Mosig, K.</creatorcontrib><creatorcontrib>Kerber, M.</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>ANTE: Abstracts in New Technology & Engineering</collection><collection>Engineering Research Database</collection><jtitle>IEEE electron device letters</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Kerber, A.</au><au>Pompl, T.</au><au>Rohner, M.</au><au>Mosig, K.</au><au>Kerber, M.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Impact of failure criteria on the reliability prediction of CMOS devices with ultrathin gate oxides based on voltage ramp stress</atitle><jtitle>IEEE electron device letters</jtitle><stitle>LED</stitle><date>2006-07-01</date><risdate>2006</risdate><volume>27</volume><issue>7</issue><spage>609</spage><epage>611</epage><pages>609-611</pages><issn>0741-3106</issn><eissn>1558-0563</eissn><coden>EDLEDZ</coden><abstract>The gate oxide reliability prediction based on the soft breakdown (SBD) failure criteria limits the operation voltage of future CMOS technologies. Progressive wear-out observed in ultrathin gate oxides leads to a delayed hard dielectric breakdown and can therefore effectively increase the reliability margin. For quantification of this effect, voltage ramp tests were applied to a large sample size and the results linked to constant voltage stress. Based on area scaling, it will be shown that a significant improvement for n- and p-FET devices is obtained when considering the area independent, uncorrelated progressive wear-out of a localized SBD spot.</abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/LED.2006.877710</doi><tpages>3</tpages></addata></record> |
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subjects | Acceleration Applied sciences Breakdown voltage CMOS CMOS technology Compound structure devices Condition monitoring Criteria Delay effects Design. Technologies. Operation analysis. Testing Devices Dielectric breakdown Electric breakdown Electric potential Electronics Exact sciences and technology Gates Integrated circuits Lead compounds MOS devices Oxides Ramps reliability Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Stress Testing Transistors Voltage |
title | Impact of failure criteria on the reliability prediction of CMOS devices with ultrathin gate oxides based on voltage ramp stress |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-28T02%3A39%3A54IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_RIE&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=Impact%20of%20failure%20criteria%20on%20the%20reliability%20prediction%20of%20CMOS%20devices%20with%20ultrathin%20gate%20oxides%20based%20on%20voltage%20ramp%20stress&rft.jtitle=IEEE%20electron%20device%20letters&rft.au=Kerber,%20A.&rft.date=2006-07-01&rft.volume=27&rft.issue=7&rft.spage=609&rft.epage=611&rft.pages=609-611&rft.issn=0741-3106&rft.eissn=1558-0563&rft.coden=EDLEDZ&rft_id=info:doi/10.1109/LED.2006.877710&rft_dat=%3Cproquest_RIE%3E2543769461%3C/proquest_RIE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=912111418&rft_id=info:pmid/&rft_ieee_id=1644842&rfr_iscdi=true |