On the effectiveness of speculative and selective memory fences

Memory fences inhibit the reordering of memory accesses in modern microprocessors; fences are useful to implement synchronization and strong shared memory semantics in multi-threaded programs. A naive implementation of memory fences can result in a significant performance penalty for processors with...

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Bibliographische Detailangaben

Hauptverfasser:	Trachsel, O., von Praun, C., Gross, T.R.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Computer science Delay Law Legal factors Memory architecture Microprocessors Monitoring Pipelines Read-write memory Yarn
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