Deep Trench Resistance and leakage Reduction - Poly1 Doping Process Optimization in High Volume DRAM Manufacturing for 300mm Factory
In this paper, we describe the influence of arsenic doped poly-silicon on signal margin and node leakage current of 110 nm deep trench DRAM products. Methods on optimizing both physical and electrical qualities of poly-silicon are presented and challenges of quick electrical characterization of the...
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| creator | Min-Soo Kim Cooper, W. Simonson, B. Ricks, D. McDaniel, E. Miller, R. Chapman, R. Taylor, T. Fuller, R. |
| description | In this paper, we describe the influence of arsenic doped poly-silicon on signal margin and node leakage current of 110 nm deep trench DRAM products. Methods on optimizing both physical and electrical qualities of poly-silicon are presented and challenges of quick electrical characterization of the new process for rapid yield learning are discussed. Finally, how these methods can be applied to other poly layers and to the next generation devices are briefly discussed |
| doi_str_mv | 10.1109/ASMC.2006.1638795 |
| format | Conference Proceeding |
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| ispartof | The 17th Annual SEMI/IEEE ASMC 2006 Conference, 2006, p.423-427 |
| issn | 1078-8743 2376-6697 |
| language | eng |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Capacitors CMOS technology Doping Furnaces Leakage current Manufacturing processes Optimization methods Production facilities Random access memory Signal processing |
| title | Deep Trench Resistance and leakage Reduction - Poly1 Doping Process Optimization in High Volume DRAM Manufacturing for 300mm Factory |
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