Loosely coupled memory-based decoding architecture for low density parity check codes

Parallel decoding is required for low density parity check (LDPC) codes to achieve high decoding throughput, but it suffers from a large set of registers and complex interconnections due to randomly located 1's in the sparse parity check matrix. This paper proposes a new LDPC decoding architect...

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Veröffentlicht in:	IEEE transactions on circuits and systems. 1, Fundamental theory and applications Fundamental theory and applications, 2006-05, Vol.53 (5), p.1045-1056
1. Verfasser:	Park, I-C
Format:	Artikel
Sprache:	eng
Schlagworte:	Algorithms Architecture Bit rate Channel coding CMOS process decoder Decoders Decoding Density factor graph Interconnections low density parity check (LDPC) code Low density parity check codes matrix permutation Memory architecture Messages Parallel architectures Parity Parity check codes Registers scheduling Scheduling algorithm Sparse matrices Studies Throughput
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