A 0.5 mu m CMOS/SOI technology
The authors describe a 0.5- mu m fully depleted CMOS technology built on thin SIMOX (separation by implanted oxygen) substrates using an accumulation mode device design for both n- and p-channel FETs. The 0.5- mu m CMOS/SOI technology has been developed for SRAM and logic applications. The circuit p...
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| creator | Edenfeld, A. Wang, L.K. Seliskar, J. Haddad, N. |
| description | The authors describe a 0.5- mu m fully depleted CMOS technology built on thin SIMOX (separation by implanted oxygen) substrates using an accumulation mode device design for both n- and p-channel FETs. The 0.5- mu m CMOS/SOI technology has been developed for SRAM and logic applications. The circuit performance is improved by 40% over an equivalent bulk CMOS as the result of the lightly doped substrate and fully depleted CMOS device design. Using a fully depleted FET design on thin SOI film can eliminate the 'kink effect' and anomalous subthreshold current caused by the floating substrate. The devices are fabricated on p-type SIMOX wafers with a thickness of 100 nm and a background doping level of approximately 1*10/sup 15/. The I-V characteristics of the n- and p-MOSFETs are shown.< > |
| doi_str_mv | 10.1109/SOI.1991.162891 |
| format | Conference Proceeding |
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The 0.5- mu m CMOS/SOI technology has been developed for SRAM and logic applications. The circuit performance is improved by 40% over an equivalent bulk CMOS as the result of the lightly doped substrate and fully depleted CMOS device design. Using a fully depleted FET design on thin SOI film can eliminate the 'kink effect' and anomalous subthreshold current caused by the floating substrate. The devices are fabricated on p-type SIMOX wafers with a thickness of 100 nm and a background doping level of approximately 1*10/sup 15/. The I-V characteristics of the n- and p-MOSFETs are shown.< ></description><identifier>ISBN: 9780780301849</identifier><identifier>ISBN: 0780301846</identifier><identifier>DOI: 10.1109/SOI.1991.162891</identifier><language>eng</language><publisher>IEEE</publisher><subject>Circuit optimization ; CMOS logic circuits ; CMOS technology ; Doping ; FETs ; Logic devices ; MOSFET circuits ; Random access memory ; Substrates ; Subthreshold current</subject><ispartof>1991 IEEE International SOI Conference Proceedings, 1991, p.130-131</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/162891$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2058,4050,4051,27925,54920</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/162891$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Edenfeld, A.</creatorcontrib><creatorcontrib>Wang, L.K.</creatorcontrib><creatorcontrib>Seliskar, J.</creatorcontrib><creatorcontrib>Haddad, N.</creatorcontrib><title>A 0.5 mu m CMOS/SOI technology</title><title>1991 IEEE International SOI Conference Proceedings</title><addtitle>SOI</addtitle><description>The authors describe a 0.5- mu m fully depleted CMOS technology built on thin SIMOX (separation by implanted oxygen) substrates using an accumulation mode device design for both n- and p-channel FETs. The 0.5- mu m CMOS/SOI technology has been developed for SRAM and logic applications. The circuit performance is improved by 40% over an equivalent bulk CMOS as the result of the lightly doped substrate and fully depleted CMOS device design. Using a fully depleted FET design on thin SOI film can eliminate the 'kink effect' and anomalous subthreshold current caused by the floating substrate. The devices are fabricated on p-type SIMOX wafers with a thickness of 100 nm and a background doping level of approximately 1*10/sup 15/. The I-V characteristics of the n- and p-MOSFETs are shown.< ></description><subject>Circuit optimization</subject><subject>CMOS logic circuits</subject><subject>CMOS technology</subject><subject>Doping</subject><subject>FETs</subject><subject>Logic devices</subject><subject>MOSFET circuits</subject><subject>Random access memory</subject><subject>Substrates</subject><subject>Subthreshold current</subject><isbn>9780780301849</isbn><isbn>0780301846</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>1991</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNpjYBA3NNAzNDSw1A_299QztLQ01DM0M7KwNGRm4LU0tzAAImMDQwsTSw4G3uLiLAMgMDE1sDQ14WSQc1Qw0DNVyC1VyFVw9vUPBpmgUJKanJGXn5OfXsnDwJqWmFOcyguluRmk3FxDnD10M1NTU-MLijJzE4sq4yGWGeOVBAAUTinK</recordid><startdate>1991</startdate><enddate>1991</enddate><creator>Edenfeld, A.</creator><creator>Wang, L.K.</creator><creator>Seliskar, J.</creator><creator>Haddad, N.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>1991</creationdate><title>A 0.5 mu m CMOS/SOI technology</title><author>Edenfeld, A. ; Wang, L.K. ; Seliskar, J. ; Haddad, N.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-ieee_primary_1628913</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>1991</creationdate><topic>Circuit optimization</topic><topic>CMOS logic circuits</topic><topic>CMOS technology</topic><topic>Doping</topic><topic>FETs</topic><topic>Logic devices</topic><topic>MOSFET circuits</topic><topic>Random access memory</topic><topic>Substrates</topic><topic>Subthreshold current</topic><toplevel>online_resources</toplevel><creatorcontrib>Edenfeld, A.</creatorcontrib><creatorcontrib>Wang, L.K.</creatorcontrib><creatorcontrib>Seliskar, J.</creatorcontrib><creatorcontrib>Haddad, N.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Edenfeld, A.</au><au>Wang, L.K.</au><au>Seliskar, J.</au><au>Haddad, N.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A 0.5 mu m CMOS/SOI technology</atitle><btitle>1991 IEEE International SOI Conference Proceedings</btitle><stitle>SOI</stitle><date>1991</date><risdate>1991</risdate><spage>130</spage><epage>131</epage><pages>130-131</pages><isbn>9780780301849</isbn><isbn>0780301846</isbn><abstract>The authors describe a 0.5- mu m fully depleted CMOS technology built on thin SIMOX (separation by implanted oxygen) substrates using an accumulation mode device design for both n- and p-channel FETs. The 0.5- mu m CMOS/SOI technology has been developed for SRAM and logic applications. The circuit performance is improved by 40% over an equivalent bulk CMOS as the result of the lightly doped substrate and fully depleted CMOS device design. Using a fully depleted FET design on thin SOI film can eliminate the 'kink effect' and anomalous subthreshold current caused by the floating substrate. The devices are fabricated on p-type SIMOX wafers with a thickness of 100 nm and a background doping level of approximately 1*10/sup 15/. The I-V characteristics of the n- and p-MOSFETs are shown.< ></abstract><pub>IEEE</pub><doi>10.1109/SOI.1991.162891</doi></addata></record> |
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| identifier | ISBN: 9780780301849 |
| ispartof | 1991 IEEE International SOI Conference Proceedings, 1991, p.130-131 |
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| language | eng |
| recordid | cdi_ieee_primary_162891 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Circuit optimization CMOS logic circuits CMOS technology Doping FETs Logic devices MOSFET circuits Random access memory Substrates Subthreshold current |
| title | A 0.5 mu m CMOS/SOI technology |
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