Clock gating methodology for high performance network processor in 90nm

As the chip geometry continues to shrink into nanometer scale, and more functionality are being added to the chip, power consumption is emerging as the no. 1 limiting source of design constraints. With the technology migrating to 90nm processing, new and more tightened design constraints have emerge...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Kok Sing Yap, Kean Hong Boey
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Clocks CMOS technology Energy consumption Geometry Intelligent networks Limiting Microelectronics Signal design Testing Timing
Online-Zugang:	Volltext bestellen
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