A DRAM/SRAM memory scheme for fast packet buffers
We address the design of high-speed packet buffers for Internet routers. We use a general DRAM/SRAM architecture for which previous proposals can be seen as particular cases. For this architecture, large SRAMs are needed to sustain high line rates and a large number of interfaces. A novel algorithm...
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| Veröffentlicht in: | IEEE transactions on computers 2006-05, Vol.55 (5), p.588-602 |
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| container_title | IEEE transactions on computers |
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| creator | Garcia-Vidal, J. March, M. Cerda, L. Corbal, J. Valero, M. |
| description | We address the design of high-speed packet buffers for Internet routers. We use a general DRAM/SRAM architecture for which previous proposals can be seen as particular cases. For this architecture, large SRAMs are needed to sustain high line rates and a large number of interfaces. A novel algorithm for DRAM bank allocation is presented that reduces the SRAM size requirements of previously proposed schemes by almost an order of magnitude, without having memory fragmentation problems. A technological evaluation shows that our design can support thousands of queues for line rates up to 160 Gbps. |
| doi_str_mv | 10.1109/TC.2006.63 |
| format | Article |
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| source | IEEE/IET Electronic Library (IEL) |
| subjects | Allocations Architecture Buffer memories Buffers Communication system routing DRAM chips Dynamic random access memory Encaminadors (Xarxes d'ordinadors) Enginyeria de la telecomunicació High speed High-performance memory systems Internet Memory architecture Packet buffers Router architecture Routers Routing (Computer network management) SRAM chips Static random access memory Storage schemes Telemàtica i xarxes d'ordinadors Àrees temàtiques de la UPC |
| title | A DRAM/SRAM memory scheme for fast packet buffers |
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