Low-leakage SRAM design with dual V/sub t/ transistors

This paper presents a method based on dual threshold voltage assignment to reduce the leakage power dissipation of SRAMs while maintaining their performance. The proposed method is based on the observation that the read and write delays of a memory cell in an SRAM block depend on the physical distan...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Amelifard, B., Fallah, F., Pedram, M.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Circuits Decoding Delay Hardware Microprocessors Power dissipation Random access memory Read-write memory Threshold voltage Very large scale integration
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!