A new FPGA packing algorithm based on the modeling method for logic block
Logic block packing is a necessary procedure of synthesis in FPGA CAD flow. In academic field, the existent packing algorithm, such as TV-Pack, is architecture-dependent and only applied to a certain type of logic blocks. In this paper, a novel function level modeling method for logic block is propo...
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| creator | Gang Ni Jiarong Tong Jinmei Lai |
| description | Logic block packing is a necessary procedure of synthesis in FPGA CAD flow. In academic field, the existent packing algorithm, such as TV-Pack, is architecture-dependent and only applied to a certain type of logic blocks. In this paper, a novel function level modeling method for logic block is proposed. Furthermore, universal pack, a universal logic block packing algorithm based on this modeling, is presented and implemented. The experimental results show that this algorithm is architecture-independent and able to deal well with different types of logic blocks. Then the modeling method is proved to be right and quite effective for logic block packing |
| doi_str_mv | 10.1109/ICASIC.2005.1611445 |
| format | Conference Proceeding |
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In academic field, the existent packing algorithm, such as TV-Pack, is architecture-dependent and only applied to a certain type of logic blocks. In this paper, a novel function level modeling method for logic block is proposed. Furthermore, universal pack, a universal logic block packing algorithm based on this modeling, is presented and implemented. The experimental results show that this algorithm is architecture-independent and able to deal well with different types of logic blocks. Then the modeling method is proved to be right and quite effective for logic block packing</description><identifier>ISSN: 2162-7541</identifier><identifier>ISBN: 9780780392106</identifier><identifier>ISBN: 0780392108</identifier><identifier>EISSN: 2162-755X</identifier><identifier>DOI: 10.1109/ICASIC.2005.1611445</identifier><language>eng</language><publisher>IEEE</publisher><subject>Circuit synthesis ; Field programmable gate arrays ; Libraries ; Logic circuits ; Logic design ; Logic devices ; Logic programming ; Microelectronics ; Signal synthesis ; Table lookup</subject><ispartof>2005 6th International Conference on ASIC, 2005, Vol.2, p.877-880</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/1611445$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>310,311,781,785,790,791,2059,4051,4052,27930,54925</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/1611445$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Gang Ni</creatorcontrib><creatorcontrib>Jiarong Tong</creatorcontrib><creatorcontrib>Jinmei Lai</creatorcontrib><title>A new FPGA packing algorithm based on the modeling method for logic block</title><title>2005 6th International Conference on ASIC</title><addtitle>ICASIC</addtitle><description>Logic block packing is a necessary procedure of synthesis in FPGA CAD flow. In academic field, the existent packing algorithm, such as TV-Pack, is architecture-dependent and only applied to a certain type of logic blocks. In this paper, a novel function level modeling method for logic block is proposed. Furthermore, universal pack, a universal logic block packing algorithm based on this modeling, is presented and implemented. The experimental results show that this algorithm is architecture-independent and able to deal well with different types of logic blocks. Then the modeling method is proved to be right and quite effective for logic block packing</description><subject>Circuit synthesis</subject><subject>Field programmable gate arrays</subject><subject>Libraries</subject><subject>Logic circuits</subject><subject>Logic design</subject><subject>Logic devices</subject><subject>Logic programming</subject><subject>Microelectronics</subject><subject>Signal synthesis</subject><subject>Table lookup</subject><issn>2162-7541</issn><issn>2162-755X</issn><isbn>9780780392106</isbn><isbn>0780392108</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2005</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNp9zs1qg0AUhuEhaaEh9QrcnBvQnGP8ySxFausukCyyCxM96tTRERVK774thC4DH7yLZ_MJ4RL6RCh3RZaeiswPECOfYqIwjFZiE1AceEkUXdbCkckBf7eXAWH89G8hvQhnnj8RkTCRMk42okhh4C_Ij-8pjKrs9NCAMo2d9NL2cFMzV2AHWFqG3lZs_rznpbUV1HYCYxtdws3YsnsVz7UyMzv3boWbv52zD08z83WcdK-m7-v98P6x_gDHFD_Z</recordid><startdate>2005</startdate><enddate>2005</enddate><creator>Gang Ni</creator><creator>Jiarong Tong</creator><creator>Jinmei Lai</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>2005</creationdate><title>A new FPGA packing algorithm based on the modeling method for logic block</title><author>Gang Ni ; Jiarong Tong ; Jinmei Lai</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-ieee_primary_16114453</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2005</creationdate><topic>Circuit synthesis</topic><topic>Field programmable gate arrays</topic><topic>Libraries</topic><topic>Logic circuits</topic><topic>Logic design</topic><topic>Logic devices</topic><topic>Logic programming</topic><topic>Microelectronics</topic><topic>Signal synthesis</topic><topic>Table lookup</topic><toplevel>online_resources</toplevel><creatorcontrib>Gang Ni</creatorcontrib><creatorcontrib>Jiarong Tong</creatorcontrib><creatorcontrib>Jinmei Lai</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Gang Ni</au><au>Jiarong Tong</au><au>Jinmei Lai</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A new FPGA packing algorithm based on the modeling method for logic block</atitle><btitle>2005 6th International Conference on ASIC</btitle><stitle>ICASIC</stitle><date>2005</date><risdate>2005</risdate><volume>2</volume><spage>877</spage><epage>880</epage><pages>877-880</pages><issn>2162-7541</issn><eissn>2162-755X</eissn><isbn>9780780392106</isbn><isbn>0780392108</isbn><abstract>Logic block packing is a necessary procedure of synthesis in FPGA CAD flow. In academic field, the existent packing algorithm, such as TV-Pack, is architecture-dependent and only applied to a certain type of logic blocks. In this paper, a novel function level modeling method for logic block is proposed. Furthermore, universal pack, a universal logic block packing algorithm based on this modeling, is presented and implemented. The experimental results show that this algorithm is architecture-independent and able to deal well with different types of logic blocks. Then the modeling method is proved to be right and quite effective for logic block packing</abstract><pub>IEEE</pub><doi>10.1109/ICASIC.2005.1611445</doi></addata></record> |
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| identifier | ISSN: 2162-7541 |
| ispartof | 2005 6th International Conference on ASIC, 2005, Vol.2, p.877-880 |
| issn | 2162-7541 2162-755X |
| language | eng |
| recordid | cdi_ieee_primary_1611445 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Circuit synthesis Field programmable gate arrays Libraries Logic circuits Logic design Logic devices Logic programming Microelectronics Signal synthesis Table lookup |
| title | A new FPGA packing algorithm based on the modeling method for logic block |
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