iSAVE: In-System Algorithm Verifier for Early-stage SoC Verification against Actual Target Environment

This paper presents a mechanism which enables verification of algorithmic-level SoC model against actual target environment. By dividing algorithmic SoC model into functional sub-model and interface sub-model and to model the behavior of the latter with FPGA-based in-circuit emulator, we can verify...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Jae-Gon Lee, Hyung-Ock Kim, Sangkwon Na, Young-Il Kim, Chong-Min Kyung
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Circuit simulation Computer bugs Decoding Electronic mail Hardware Network address translation Process design Software debugging Testing Timing
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