65nm cmos technology for low power applications

This paper presents a 65nm low power technology offering a dual gate oxide process, multiple Vt devices at a nominal operating voltage of 1.2V, a nine level hierarchical Cu interconnect back-end of line process with low k dielectrics and 0.676mum 2 and 0.54mum 2 SRAM cells, optimized for performance...

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Hauptverfasser:	Steegen, A., Mo, R., Mann, R., Sun, M.-C., Eller, M., Leake, G., Vietzke, D., Tilke, A., Guarin, F., Fischer, A., Pompl, T., Massey, G., Vayshenker, A., Tan, W.L., Ebert, A., Lin, W., Gao, W., Lian, J., Kim, J.-P., Wrschka, P., Yang, J.-H., Ajmera, A., Knoefler, R., Teh, Y.-W., Jamin, F., Park, J.E., Hooper, K., Griffin, C., Nguyen, P., Klee, V., Ku, V., Baiocco, C., Johnson, G., Tai, L., Benedict, J., Scheer, S., Zhuang, H., Ramanchandran, V., Matusiewicz, G., Lin, Y.-H., Siew, Y.K., Zhang, F., Leong, L.S., Liew, S.L., Park, K.C., Lee, K.-W., Hong, D.H., Choi, S.-M., Kaltalioglu, E., Kim, S.O., Naujok, M., Sherony, M., Cowley, A., Thomas, A., Sudijohno, J., Schiml, T., Ku, J.-H., Yang, I.
Format:	Tagungsbericht
Sprache:	eng ; jpn
Schlagworte:	CMOS logic circuits CMOS technology Costs Implants Integrated circuit technology Isolation technology Leakage current Random access memory Space technology Voltage
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