Resynthesis of multi-phase pipelines

This paper describes an algorithm for deriving necessary and sufficient constraints for a multi-phase sequential pipeline to operate at a target clock cycle. Constraints on delays of the pipeline stages are used to drive a combinational logic delay optimizer to resynthesize the pipeline stages for improved performance. A main advantage of such an approach is that a global picture of the distribution of delays in the circuit is obtained. It also permits safe cycle stealing through level-sensitive latches across pipeline stages.