An SPU reference model for simulation, random test generation and verification

An instruction set level reference model was developed for the development of synergistic processing unit (SPU), which is one of the key components of the cell processor [Pham, 2005][Flachs, 2005]. This reference model was used for the simulators to define the instruction set architecture (ISA), for...

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Bibliographische Detailangaben

Hauptverfasser:	Watanabe, Y., Sallay, B., Michael, B., Brokenshire, D., Meil, G., Hazim Shafi, Hiraoka, D.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Computer architecture Computer bugs Decoding Instruction sets Microprocessors Programming Registers Robustness Software testing Streaming media
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