PowerViP: SoC power estimation framework at transaction level

PowerViP: SoC power estimation framework at transaction level

In this work, we propose a SoC power estimation framework built on our system-level simulation environment. Our framework provides designers with the system-level power profile in a cycle-accurate manner. We target the framework to run fast and accurately, which is enabled by adopting different mode...

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Hauptverfasser: Ikhwan Lee, Hyunsuk Kim, Peng Yang, Sungjoo Yoo, Eui-Young Chung, Kyu-Myung Choi, Jeong-Taek Kong, Soo-Kwan Eo
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Boosting
Energy consumption
Fabrics
Power generation
Power system modeling
Random access memory
Space exploration
System-level design
System-on-a-chip
Video codecs
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Beschreibung
Zusammenfassung:In this work, we propose a SoC power estimation framework built on our system-level simulation environment. Our framework provides designers with the system-level power profile in a cycle-accurate manner. We target the framework to run fast and accurately, which is enabled by adopting different modeling techniques depending on the power characteristics of various IP blocks. The framework can be applied to any target SoC design
ISSN:2153-6961
2153-697X
DOI:10.1109/ASPDAC.2006.1594743