ePAPP: a gigabit embedded protocol analyzer pre-processor
Network has been growing rapidly in both transmission bandwidth and transmission speed. This increase in speed reduces processing time a network device has for each packet. This paper presents a hardware embedded protocol analyzer pre-processor (ePAPP) that performs the protocol analysis of network...
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creator | Hoare, R.R. Ying Yu Repanshek, J.J. |
description | Network has been growing rapidly in both transmission bandwidth and transmission speed. This increase in speed reduces processing time a network device has for each packet. This paper presents a hardware embedded protocol analyzer pre-processor (ePAPP) that performs the protocol analysis of network packets. It replaces the software protocol analysis program running on processors, with a significant performance increase, and protocol adaptation flexibility. A prototype of ePAPP supporting various protocols including Ethernet, IPv4, ARP, TCP, and UDP, has been designed in VHDL and synthesized. When implemented on the NEC instant silicon solutions platform (ISSP), a structured ASIC technology based on 0.13-micron process, ePPAP can achieve 2.88 Gb/s processing rate, using less than 1% of available logic cells. |
doi_str_mv | 10.1109/MWSCAS.2005.1594039 |
format | Conference Proceeding |
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This increase in speed reduces processing time a network device has for each packet. This paper presents a hardware embedded protocol analyzer pre-processor (ePAPP) that performs the protocol analysis of network packets. It replaces the software protocol analysis program running on processors, with a significant performance increase, and protocol adaptation flexibility. A prototype of ePAPP supporting various protocols including Ethernet, IPv4, ARP, TCP, and UDP, has been designed in VHDL and synthesized. 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This increase in speed reduces processing time a network device has for each packet. This paper presents a hardware embedded protocol analyzer pre-processor (ePAPP) that performs the protocol analysis of network packets. It replaces the software protocol analysis program running on processors, with a significant performance increase, and protocol adaptation flexibility. A prototype of ePAPP supporting various protocols including Ethernet, IPv4, ARP, TCP, and UDP, has been designed in VHDL and synthesized. When implemented on the NEC instant silicon solutions platform (ISSP), a structured ASIC technology based on 0.13-micron process, ePPAP can achieve 2.88 Gb/s processing rate, using less than 1% of available logic cells.</description><subject>Bandwidth</subject><subject>Ethernet networks</subject><subject>Hardware</subject><subject>National electric code</subject><subject>Network synthesis</subject><subject>Performance analysis</subject><subject>Protocols</subject><subject>Prototypes</subject><subject>Software performance</subject><subject>Software prototyping</subject><issn>1548-3746</issn><issn>1558-3899</issn><isbn>9780780391970</isbn><isbn>0780391977</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2005</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotj91Kw0AUhBd_wFr7BL3JCySes7vJ7vEuFK1CxUALXpaT7EmJpKYkualPb8TCwAzfwMAotURIEIEe3z-3q3ybaIA0wZQsGLpSM0xTHxtPdK0W5DxMMoTk4Oavs1PnbHan7ofhC0AbhzRTJEVeFE8RR4fmwGUzRnIsJQQJ0anvxq7q2oi_uT3_SD8RiSdayTB0_YO6rbkdZHHxudq9PO9Wr_HmY_22yjdxQzDGIWSG0YNoYufIerC11uxdHaqaRaosSxnBB4-mthDEl8HYYDXaKYOYuVr-zzYisj_1zZH78_5y2vwCy_tJVQ</recordid><startdate>2005</startdate><enddate>2005</enddate><creator>Hoare, R.R.</creator><creator>Ying Yu</creator><creator>Repanshek, J.J.</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>2005</creationdate><title>ePAPP: a gigabit embedded protocol analyzer pre-processor</title><author>Hoare, R.R. ; Ying Yu ; Repanshek, J.J.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i90t-dd63a180e29a7794804f22a87fdcfaeec665a108d813f40de8bd34d4214de80e3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2005</creationdate><topic>Bandwidth</topic><topic>Ethernet networks</topic><topic>Hardware</topic><topic>National electric code</topic><topic>Network synthesis</topic><topic>Performance analysis</topic><topic>Protocols</topic><topic>Prototypes</topic><topic>Software performance</topic><topic>Software prototyping</topic><toplevel>online_resources</toplevel><creatorcontrib>Hoare, R.R.</creatorcontrib><creatorcontrib>Ying Yu</creatorcontrib><creatorcontrib>Repanshek, J.J.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Hoare, R.R.</au><au>Ying Yu</au><au>Repanshek, J.J.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>ePAPP: a gigabit embedded protocol analyzer pre-processor</atitle><btitle>48th Midwest Symposium on Circuits and Systems, 2005</btitle><stitle>MWSCAS</stitle><date>2005</date><risdate>2005</risdate><spage>59</spage><epage>62 Vol. 1</epage><pages>59-62 Vol. 1</pages><issn>1548-3746</issn><eissn>1558-3899</eissn><isbn>9780780391970</isbn><isbn>0780391977</isbn><abstract>Network has been growing rapidly in both transmission bandwidth and transmission speed. This increase in speed reduces processing time a network device has for each packet. This paper presents a hardware embedded protocol analyzer pre-processor (ePAPP) that performs the protocol analysis of network packets. It replaces the software protocol analysis program running on processors, with a significant performance increase, and protocol adaptation flexibility. A prototype of ePAPP supporting various protocols including Ethernet, IPv4, ARP, TCP, and UDP, has been designed in VHDL and synthesized. When implemented on the NEC instant silicon solutions platform (ISSP), a structured ASIC technology based on 0.13-micron process, ePPAP can achieve 2.88 Gb/s processing rate, using less than 1% of available logic cells.</abstract><pub>IEEE</pub><doi>10.1109/MWSCAS.2005.1594039</doi></addata></record> |
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subjects | Bandwidth Ethernet networks Hardware National electric code Network synthesis Performance analysis Protocols Prototypes Software performance Software prototyping |
title | ePAPP: a gigabit embedded protocol analyzer pre-processor |
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