Real-time FPGA-based architecture for bicubic interpolation: an application for digital image scaling

One of the most extended algorithms for image scaling is bicubic interpolation. In this paper, a hardware architecture for bicubic interpolation (HABI) is proposed. The HABI proposed is integrated by three main blocks: the first one generates the interpolation coefficients, which implements the bicu...

Ausführliche Beschreibung

Gespeichert in:

Bibliographische Detailangaben
Hauptverfasser:	Nuno-Maganda, M.A., Arias-Estrada, M.O.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Application software Brightness Computer architecture Digital images Field programmable gate arrays Hardware Image processing Interpolation Microprocessors Pipelines
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!

container_end_page	1
container_issue
container_start_page	8 pp.
container_title
container_volume
creator	Nuno-Maganda, M.A. Arias-Estrada, M.O.
description	One of the most extended algorithms for image scaling is bicubic interpolation. In this paper, a hardware architecture for bicubic interpolation (HABI) is proposed. The HABI proposed is integrated by three main blocks: the first one generates the interpolation coefficients, which implements the bicubic function to be used in HABI; the second one performs the interpolation process and the third one is a control unit that synchronizes the processing and the pipeline stages. The architecture work with monochromatic images, but it can be extended for working with RGB color images. Our design description is coded in Handel-C language and implemented on a Xilinx Virtex II Pro FPGA. The proposed system runs 10 times faster than an Intel Pentium 4-based PC at 2.4 GHz. Comparison with other related works are provided
doi_str_mv	10.1109/RECONFIG.2005.34
format	Conference Proceeding
fullrecord	<record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_1592483</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>1592483</ieee_id><sourcerecordid>1592483</sourcerecordid><originalsourceid>FETCH-LOGICAL-i241t-78d27584151a8210717356cc58a2688376f84b1e67b5f4c295667112df7d42ef3</originalsourceid><addsrcrecordid>eNotTktLw0AYXHyAtfYueNk_sHX322e8ldDWQrFS9Fw2my91JU1Csj347w3VgWEYZhiGkEfB50Lw7Hm_zHdvq816DpzruVRXZAJGccaVhWtyz63JNCht7M0YSNDMaAl3ZDYM33yEzAx3ZkJwj75mKZ6Qrt7XC1b4AUvq-_AVE4Z07pFWbU-LGM4jaWwS9l1b-xTb5oX6hvquq2O4-EuzjMeYfE3jyR-RDsHXsTk-kNvK1wPO_nVKPlfLj_yVbXfrTb7YsghKJGZdCVY7JbTwDgS3wkptQtDOg3FOWlM5VQg0ttCVCpBpY6wQUFa2VICVnJKnv92IiIeuH0_0PwehM1BOyl8NYVdt</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Real-time FPGA-based architecture for bicubic interpolation: an application for digital image scaling</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Nuno-Maganda, M.A. ; Arias-Estrada, M.O.</creator><creatorcontrib>Nuno-Maganda, M.A. ; Arias-Estrada, M.O.</creatorcontrib><description>One of the most extended algorithms for image scaling is bicubic interpolation. In this paper, a hardware architecture for bicubic interpolation (HABI) is proposed. The HABI proposed is integrated by three main blocks: the first one generates the interpolation coefficients, which implements the bicubic function to be used in HABI; the second one performs the interpolation process and the third one is a control unit that synchronizes the processing and the pipeline stages. The architecture work with monochromatic images, but it can be extended for working with RGB color images. Our design description is coded in Handel-C language and implemented on a Xilinx Virtex II Pro FPGA. The proposed system runs 10 times faster than an Intel Pentium 4-based PC at 2.4 GHz. Comparison with other related works are provided</description><identifier>ISSN: 2325-6532</identifier><identifier>ISBN: 0769524567</identifier><identifier>ISBN: 9780769524566</identifier><identifier>EISSN: 2640-0472</identifier><identifier>DOI: 10.1109/RECONFIG.2005.34</identifier><language>eng</language><publisher>IEEE</publisher><subject>Application software ; Brightness ; Computer architecture ; Digital images ; Field programmable gate arrays ; Hardware ; Image processing ; Interpolation ; Microprocessors ; Pipelines</subject><ispartof>2005 International Conference on Reconfigurable Computing and FPGAs (ReConFig'05), 2005, p.8 pp.-1</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/1592483$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,776,780,785,786,2052,4036,4037,27902,54895</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/1592483$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Nuno-Maganda, M.A.</creatorcontrib><creatorcontrib>Arias-Estrada, M.O.</creatorcontrib><title>Real-time FPGA-based architecture for bicubic interpolation: an application for digital image scaling</title><title>2005 International Conference on Reconfigurable Computing and FPGAs (ReConFig'05)</title><addtitle>RECONF</addtitle><description>One of the most extended algorithms for image scaling is bicubic interpolation. In this paper, a hardware architecture for bicubic interpolation (HABI) is proposed. The HABI proposed is integrated by three main blocks: the first one generates the interpolation coefficients, which implements the bicubic function to be used in HABI; the second one performs the interpolation process and the third one is a control unit that synchronizes the processing and the pipeline stages. The architecture work with monochromatic images, but it can be extended for working with RGB color images. Our design description is coded in Handel-C language and implemented on a Xilinx Virtex II Pro FPGA. The proposed system runs 10 times faster than an Intel Pentium 4-based PC at 2.4 GHz. Comparison with other related works are provided</description><subject>Application software</subject><subject>Brightness</subject><subject>Computer architecture</subject><subject>Digital images</subject><subject>Field programmable gate arrays</subject><subject>Hardware</subject><subject>Image processing</subject><subject>Interpolation</subject><subject>Microprocessors</subject><subject>Pipelines</subject><issn>2325-6532</issn><issn>2640-0472</issn><isbn>0769524567</isbn><isbn>9780769524566</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2005</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotTktLw0AYXHyAtfYueNk_sHX322e8ldDWQrFS9Fw2my91JU1Csj347w3VgWEYZhiGkEfB50Lw7Hm_zHdvq816DpzruVRXZAJGccaVhWtyz63JNCht7M0YSNDMaAl3ZDYM33yEzAx3ZkJwj75mKZ6Qrt7XC1b4AUvq-_AVE4Z07pFWbU-LGM4jaWwS9l1b-xTb5oX6hvquq2O4-EuzjMeYfE3jyR-RDsHXsTk-kNvK1wPO_nVKPlfLj_yVbXfrTb7YsghKJGZdCVY7JbTwDgS3wkptQtDOg3FOWlM5VQg0ttCVCpBpY6wQUFa2VICVnJKnv92IiIeuH0_0PwehM1BOyl8NYVdt</recordid><startdate>2005</startdate><enddate>2005</enddate><creator>Nuno-Maganda, M.A.</creator><creator>Arias-Estrada, M.O.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>2005</creationdate><title>Real-time FPGA-based architecture for bicubic interpolation: an application for digital image scaling</title><author>Nuno-Maganda, M.A. ; Arias-Estrada, M.O.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i241t-78d27584151a8210717356cc58a2688376f84b1e67b5f4c295667112df7d42ef3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2005</creationdate><topic>Application software</topic><topic>Brightness</topic><topic>Computer architecture</topic><topic>Digital images</topic><topic>Field programmable gate arrays</topic><topic>Hardware</topic><topic>Image processing</topic><topic>Interpolation</topic><topic>Microprocessors</topic><topic>Pipelines</topic><toplevel>online_resources</toplevel><creatorcontrib>Nuno-Maganda, M.A.</creatorcontrib><creatorcontrib>Arias-Estrada, M.O.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Nuno-Maganda, M.A.</au><au>Arias-Estrada, M.O.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Real-time FPGA-based architecture for bicubic interpolation: an application for digital image scaling</atitle><btitle>2005 International Conference on Reconfigurable Computing and FPGAs (ReConFig'05)</btitle><stitle>RECONF</stitle><date>2005</date><risdate>2005</risdate><spage>8 pp.</spage><epage>1</epage><pages>8 pp.-1</pages><issn>2325-6532</issn><eissn>2640-0472</eissn><isbn>0769524567</isbn><isbn>9780769524566</isbn><abstract>One of the most extended algorithms for image scaling is bicubic interpolation. In this paper, a hardware architecture for bicubic interpolation (HABI) is proposed. The HABI proposed is integrated by three main blocks: the first one generates the interpolation coefficients, which implements the bicubic function to be used in HABI; the second one performs the interpolation process and the third one is a control unit that synchronizes the processing and the pipeline stages. The architecture work with monochromatic images, but it can be extended for working with RGB color images. Our design description is coded in Handel-C language and implemented on a Xilinx Virtex II Pro FPGA. The proposed system runs 10 times faster than an Intel Pentium 4-based PC at 2.4 GHz. Comparison with other related works are provided</abstract><pub>IEEE</pub><doi>10.1109/RECONFIG.2005.34</doi></addata></record>
fulltext	fulltext_linktorsrc
identifier	ISSN: 2325-6532
ispartof	2005 International Conference on Reconfigurable Computing and FPGAs (ReConFig'05), 2005, p.8 pp.-1
issn	2325-6532 2640-0472
language	eng
recordid	cdi_ieee_primary_1592483
source	IEEE Electronic Library (IEL) Conference Proceedings
subjects	Application software Brightness Computer architecture Digital images Field programmable gate arrays Hardware Image processing Interpolation Microprocessors Pipelines
title	Real-time FPGA-based architecture for bicubic interpolation: an application for digital image scaling
url	https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-28T23%3A31%3A59IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Real-time%20FPGA-based%20architecture%20for%20bicubic%20interpolation:%20an%20application%20for%20digital%20image%20scaling&rft.btitle=2005%20International%20Conference%20on%20Reconfigurable%20Computing%20and%20FPGAs%20(ReConFig'05)&rft.au=Nuno-Maganda,%20M.A.&rft.date=2005&rft.spage=8%20pp.&rft.epage=1&rft.pages=8%20pp.-1&rft.issn=2325-6532&rft.eissn=2640-0472&rft.isbn=0769524567&rft.isbn_list=9780769524566&rft_id=info:doi/10.1109/RECONFIG.2005.34&rft_dat=%3Cieee_6IE%3E1592483%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=1592483&rfr_iscdi=true