An Algorithm for Finding a Rectangular Dual of a Planar Graph for Use in Area Planning for VLSI Integrated Circuits

An O(n /sup 2/) algorithm for finding a rectangular dual of a planar triangulated graph is presented. In practice, almost linear running times have been observed. The algorithm is useful for solving area planning problems in VLSI IC design.

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Bibliographische Detailangaben
Hauptverfasser:	Kozminski, K., Kinnen, E.
Format:	Tagungsbericht
Sprache:	eng ; jpn
Schlagworte:	Algorithm design and analysis Clustering algorithms Integrated circuit interconnections Integrated circuit layout Polynomials Sufficient conditions Very large scale integration
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Beschreibung
Zusammenfassung:	An O(n /sup 2/) algorithm for finding a rectangular dual of a planar triangulated graph is presented. In practice, almost linear running times have been observed. The algorithm is useful for solving area planning problems in VLSI IC design.
ISSN:	0738-100X
DOI:	10.1109/DAC.1984.1585872