Test pattern optimization using proper in mixed-mode technique

This paper presents a test pattern optimization approach using a proper number of seed selection in mixed-mode patterns. In mixed-mode patterns, the test set is assembled from LFSR based pseudorandom and deterministic patterns. The efficiency of this approach is largely determined by the ratio of th...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Syed Zahidul Islam, Mohd Alauddin Mohd Ali
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Assembly Circuit faults Circuit testing Cost function Digital systems Hardware Integrated circuit testing Linear feedback shift registers System testing Test pattern generators
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