Low Cost Delay Testing of Nanometer SoCs Using On-Chip Clocking and Test Compression

Testing at-speed delay defects is difficult on a speed constrained low cost tester. This paper describes the use of a clock chopper based onproduct clocking circuitry and interfaces to delay ATPG to achieve reliable test patterns. We also describe the test compression methods used to address the pro...

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Bibliographische Detailangaben

Hauptverfasser:	Nakamura, H., Shirokane, A., Nishizaki, Y., Uzzaman, A., Chickermane, V., Keller, B., Ube, T., Terauchi, Y.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Automatic test pattern generation Circuit faults Circuit testing Clocks Costs Delay Nanoscale devices System testing System-on-a-chip Timing
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