A conditional clocking flip-flop for low power H.264/MPEG-4 audio/visual codec LSI

A conditional clocking flip-flop for low power H.264/MPEG-4 audio/visual codec LSI

A novel conditional clocking flip-flop is proposed. The flip-flop circuit does not consume any power when the data input of the flip-flop does not change its state. Taking the overhead of the auxiliary circuits into account, the flip-flop consumes less power than the conventional flip-flop when the...

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Bibliographische Detailangaben
Hauptverfasser: Hamada, M., Hara, H., Fujita, T., Chen Kong Teh, Shimazawa, T., Kawabe, N., Kitahara, T., Kikuchi, Y., Nishikawa, T., Takahashi, M., Oowaki, Y.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Circuit testing
Clocks
Codecs
Delay
Energy consumption
Flip-flops
Large scale integration
Latches
Master-slave
MPEG 4 Standard
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Beschreibung
Zusammenfassung:A novel conditional clocking flip-flop is proposed. The flip-flop circuit does not consume any power when the data input of the flip-flop does not change its state. Taking the overhead of the auxiliary circuits into account, the flip-flop consumes less power than the conventional flip-flop when the data transition probability is less than 55%. By employing the conditional clocking flip-flop circuits in a mobile applications LSI, the power consumption is reduced by 8-31%.
ISSN:0886-5930
2152-3630
DOI:10.1109/CICC.2005.1568722