An integrated timing and dynamic supply noise verification for nano-meter CMOS SoC designs

A semidynamic timing analysis flow of dynamic drop consideration applicable to a large-scale circuit is proposed. This technique is compared not only with SPICE simulation but with measurements using built-in noise probing and on-chip delay monitoring techniques, which validates the proposed flow.

Bibliographische Detailangaben

Hauptverfasser:	Shimazaki, K., Fukazawa, M., Nagata, M., Miyahara, S., Hirata, M., Sato, K., Tsujikawa, H.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Circuit noise Delay estimation Integrated circuit noise Large-scale systems Logic Noise measurement Power supplies Semiconductor device measurement Timing Voltage
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!