Performance of sorting algorithms on the SRC 6 reconfigurable computer

The execution speed of the FPGA processing elements are compared to the microprocessor processing elements in the SRC 6 reconfigurable computer using the following algorithms for sorting: quick sort, heap sort, radix sort, bitonic sort, and odd/even merge. The results show that, for sorting, FPGA te...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Harkins, J., El-Ghazawi, T., El-Araby, E., Huang, M.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Bandwidth Clocks Field programmable gate arrays Hardware High performance computing Microprocessors Pipeline processing Sorting System performance Upper bound
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