Extensible linear floating point SIMD neurocomputer array processor
A 32-bit IEEE floating-point-format single-input-multiple-data (SIMD array processor) connected in a linear ring structure has been designed for neural network applications. The first prototype is composed of a SIMD array of between 16 and 64 cells. Each cell in the array is capable of simultaneousl...
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| container_end_page | 592 vol.1 |
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| creator | Means, R.W. Lisenbee, L. |
| description | A 32-bit IEEE floating-point-format single-input-multiple-data (SIMD array processor) connected in a linear ring structure has been designed for neural network applications. The first prototype is composed of a SIMD array of between 16 and 64 cells. Each cell in the array is capable of simultaneously performing 20 million floating point multiplications and 20 million floating point arithmetic operations per second. This gives the prototype a peak processing performance of between 640 and 2560 MFLOPS. This compact array processor uses VLSI technology to produce four 32-bit cells per chip and off-the-shelf bit-slice components to assemble the controller. The hardware architecture of the SIMD neurocomputer array processor systolic array processor is described.< > |
| doi_str_mv | 10.1109/IJCNN.1991.155243 |
| format | Conference Proceeding |
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The hardware architecture of the SIMD neurocomputer array processor systolic array processor is described.< ></description><identifier>ISBN: 0780301641</identifier><identifier>ISBN: 9780780301641</identifier><identifier>DOI: 10.1109/IJCNN.1991.155243</identifier><language>eng</language><publisher>IEEE</publisher><subject>Application software ; Assembly ; Computer architecture ; Coprocessors ; Costs ; Floating-point arithmetic ; Neural networks ; Prototypes ; Research and development ; Very large scale integration</subject><ispartof>IJCNN-91-Seattle International Joint Conference on Neural Networks, 1991, Vol.i, p.587-592 vol.1</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/155243$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2058,4050,4051,27925,54920</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/155243$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Means, R.W.</creatorcontrib><creatorcontrib>Lisenbee, L.</creatorcontrib><title>Extensible linear floating point SIMD neurocomputer array processor</title><title>IJCNN-91-Seattle International Joint Conference on Neural Networks</title><addtitle>IJCNN</addtitle><description>A 32-bit IEEE floating-point-format single-input-multiple-data (SIMD array processor) connected in a linear ring structure has been designed for neural network applications. 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The hardware architecture of the SIMD neurocomputer array processor systolic array processor is described.< ></description><subject>Application software</subject><subject>Assembly</subject><subject>Computer architecture</subject><subject>Coprocessors</subject><subject>Costs</subject><subject>Floating-point arithmetic</subject><subject>Neural networks</subject><subject>Prototypes</subject><subject>Research and development</subject><subject>Very large scale integration</subject><isbn>0780301641</isbn><isbn>9780780301641</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>1991</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotj81Kw0AUhQdEUGsfQFfzAo33TuYns5RYbaTWhbouk-SOjKRJmEnBvr2BejYHvsXhO4zdIWSIYB-q13K3y9BazFApIfMLdgOmgBxQS7xiy5R-YI5UoFVxzcr170R9CnVHvAs9uch9N7gp9N98HEI_8Y_q7Yn3dIxDMxzG40SRuxjdiY8zoZSGeMsuvesSLf97wb6e15_lZrV9f6nKx-0qoBHTSptWkWglGAlSt94XBrWCGryaVWtdoGvzxgothLZKC2isd61viIxx5Gy-YPfn3UBE-zGGg4un_flm_gfZ8Ejv</recordid><startdate>1991</startdate><enddate>1991</enddate><creator>Means, R.W.</creator><creator>Lisenbee, L.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>1991</creationdate><title>Extensible linear floating point SIMD neurocomputer array processor</title><author>Means, R.W. ; Lisenbee, L.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i172t-67d5e2d4074046dff871650b0f5155b681ad3c92622695620c9fadfcee77aea93</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>1991</creationdate><topic>Application software</topic><topic>Assembly</topic><topic>Computer architecture</topic><topic>Coprocessors</topic><topic>Costs</topic><topic>Floating-point arithmetic</topic><topic>Neural networks</topic><topic>Prototypes</topic><topic>Research and development</topic><topic>Very large scale integration</topic><toplevel>online_resources</toplevel><creatorcontrib>Means, R.W.</creatorcontrib><creatorcontrib>Lisenbee, L.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Means, R.W.</au><au>Lisenbee, L.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Extensible linear floating point SIMD neurocomputer array processor</atitle><btitle>IJCNN-91-Seattle International Joint Conference on Neural Networks</btitle><stitle>IJCNN</stitle><date>1991</date><risdate>1991</risdate><volume>i</volume><spage>587</spage><epage>592 vol.1</epage><pages>587-592 vol.1</pages><isbn>0780301641</isbn><isbn>9780780301641</isbn><abstract>A 32-bit IEEE floating-point-format single-input-multiple-data (SIMD array processor) connected in a linear ring structure has been designed for neural network applications. The first prototype is composed of a SIMD array of between 16 and 64 cells. Each cell in the array is capable of simultaneously performing 20 million floating point multiplications and 20 million floating point arithmetic operations per second. This gives the prototype a peak processing performance of between 640 and 2560 MFLOPS. This compact array processor uses VLSI technology to produce four 32-bit cells per chip and off-the-shelf bit-slice components to assemble the controller. The hardware architecture of the SIMD neurocomputer array processor systolic array processor is described.< ></abstract><pub>IEEE</pub><doi>10.1109/IJCNN.1991.155243</doi></addata></record> |
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| identifier | ISBN: 0780301641 |
| ispartof | IJCNN-91-Seattle International Joint Conference on Neural Networks, 1991, Vol.i, p.587-592 vol.1 |
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| language | eng |
| recordid | cdi_ieee_primary_155243 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Application software Assembly Computer architecture Coprocessors Costs Floating-point arithmetic Neural networks Prototypes Research and development Very large scale integration |
| title | Extensible linear floating point SIMD neurocomputer array processor |
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