A low-power 22-bit incremental ADC with 4 ppm INL, 2 ppm gain error and 2 /spl mu/V DC offset

A low power 22bit incremental ADC, including an on-chip digital filter and a low noise/low drift oscillator, was realized in a 0.6-/spl mu/m CMOS process. It incorporates a novel offset cancellation scheme based on fractal sequences, a novel high accuracy gain control circuit, and a novel reduced co...

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Bibliographische Detailangaben

Hauptverfasser:	Quiquempoix, V., Deval, P., Barreto, A., Bellini, G., Collings, J., Markus, J., Silva, J., Temes, G.C.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Circuit noise CMOS process Digital filters Fractals Gain control Gain measurement Noise cancellation Noise measurement Oscillators Semiconductor device measurement
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