Proteus system architecture and organization

The Proteus architecture is a highly parallel MIMD, multiple instruction multiple data, machine optimized for large granularity tasks such as machine vision and image processing. The system can achieve 20 G-flops (80 G-flops peak). It accepts data via multiple serial links at a rate of up to 640 meg...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Somani, A.K., Wittenbrink, C., Haralick, R.M., Shapiro, L.G., Jenq-Neng Hwang, Chung-Ho Chen, Johnson, R., Cooper, K.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Circuit faults Electrical fault detection Fault detection Hardware Hypercubes Image processing Machine vision Multiprocessor interconnection networks Reduced instruction set computing Switching circuits
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