Collector optimization in advanced SiGe HBT technologies
With the advancement of the fT/fMAX performance scaling of SiGe HBTs the breakdown voltage (BVCBO/BVCEO) reduces commensurately, causing design related concerns. It is important, therefore, that multiple fT/BVCEO devices be offered in the RF technologies to meet the varying needs of the communicatio...
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| creator | Liu, Q.Z. Orner, B.A. Lanzerotti, L. Dahlstrom, M. Hodge, W. Gordon, M. Johnson, J. Gautsch, M. Greco, J. Rascoe, J. Ahlgren, D. Joseph, A. Dunn, J. |
| description | With the advancement of the fT/fMAX performance scaling of SiGe HBTs the breakdown voltage (BVCBO/BVCEO) reduces commensurately, causing design related concerns. It is important, therefore, that multiple fT/BVCEO devices be offered in the RF technologies to meet the varying needs of the communication products. Unlike the GaAs technologies, the SiGe BiCMOS technologies are capable of integrating various flavors of fT/BVCEO SiGe HBT devices at a technology node. In this work, we investigate the tradeoff in fT-BVCEO for advanced SiGe HBTs by various collector optimization schemes such as, subcollector dopant species and concentration, epilayer thickness, SIC and other layout techniques. |
| doi_str_mv | 10.1109/CSICS.2005.1531779 |
| format | Conference Proceeding |
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It is important, therefore, that multiple fT/BVCEO devices be offered in the RF technologies to meet the varying needs of the communication products. Unlike the GaAs technologies, the SiGe BiCMOS technologies are capable of integrating various flavors of fT/BVCEO SiGe HBT devices at a technology node. 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In this work, we investigate the tradeoff in fT-BVCEO for advanced SiGe HBTs by various collector optimization schemes such as, subcollector dopant species and concentration, epilayer thickness, SIC and other layout techniques.</description><subject>BiCMOS integrated circuits</subject><subject>CMOS technology</subject><subject>Delay</subject><subject>Design optimization</subject><subject>Doping</subject><subject>Electric breakdown</subject><subject>Germanium silicon alloys</subject><subject>Heterojunction bipolar transistors</subject><subject>Silicon carbide</subject><subject>Silicon germanium</subject><issn>1550-8781</issn><issn>2374-8443</issn><isbn>0780392507</isbn><isbn>9780780392502</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2005</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotj8tKw0AYRgcvYFp9Ad3MCyT-c59ZatC2UHCRui6TmT86kmZKEgR9egt29R04cOAj5J5BxRi4x7rZ1E3FAVTFlGDGuAtScGFkaaUUl2QBxoJwXIG5IgVTCkprLLshi2n6AhAnNgWxde57DHMeaT7O6ZB-_ZzyQNNAffz2Q8BIm7RCun7e0RnD55D7_JFwuiXXne8nvDvvkry_vuzqdbl9W23qp22ZmFFzaWQbW43AuVBBK2mDjgFOKnSCW60ihg6Dc1pag61gTsfYii4yENyDbsWSPPx3EyLuj2M6-PFnf34s_gDO0kgR</recordid><startdate>2005</startdate><enddate>2005</enddate><creator>Liu, Q.Z.</creator><creator>Orner, B.A.</creator><creator>Lanzerotti, L.</creator><creator>Dahlstrom, M.</creator><creator>Hodge, W.</creator><creator>Gordon, M.</creator><creator>Johnson, J.</creator><creator>Gautsch, M.</creator><creator>Greco, J.</creator><creator>Rascoe, J.</creator><creator>Ahlgren, D.</creator><creator>Joseph, A.</creator><creator>Dunn, J.</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>2005</creationdate><title>Collector optimization in advanced SiGe HBT technologies</title><author>Liu, Q.Z. ; Orner, B.A. ; Lanzerotti, L. ; Dahlstrom, M. ; Hodge, W. ; Gordon, M. ; Johnson, J. ; Gautsch, M. ; Greco, J. ; Rascoe, J. ; Ahlgren, D. ; Joseph, A. ; Dunn, J.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-74bdb6e02235c6548c6dc0175cf32865decfec996487eb3196ddb3fd1032a06b3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2005</creationdate><topic>BiCMOS integrated circuits</topic><topic>CMOS technology</topic><topic>Delay</topic><topic>Design optimization</topic><topic>Doping</topic><topic>Electric breakdown</topic><topic>Germanium silicon alloys</topic><topic>Heterojunction bipolar transistors</topic><topic>Silicon carbide</topic><topic>Silicon germanium</topic><toplevel>online_resources</toplevel><creatorcontrib>Liu, Q.Z.</creatorcontrib><creatorcontrib>Orner, B.A.</creatorcontrib><creatorcontrib>Lanzerotti, L.</creatorcontrib><creatorcontrib>Dahlstrom, M.</creatorcontrib><creatorcontrib>Hodge, W.</creatorcontrib><creatorcontrib>Gordon, M.</creatorcontrib><creatorcontrib>Johnson, J.</creatorcontrib><creatorcontrib>Gautsch, M.</creatorcontrib><creatorcontrib>Greco, J.</creatorcontrib><creatorcontrib>Rascoe, J.</creatorcontrib><creatorcontrib>Ahlgren, D.</creatorcontrib><creatorcontrib>Joseph, A.</creatorcontrib><creatorcontrib>Dunn, J.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Liu, Q.Z.</au><au>Orner, B.A.</au><au>Lanzerotti, L.</au><au>Dahlstrom, M.</au><au>Hodge, W.</au><au>Gordon, M.</au><au>Johnson, J.</au><au>Gautsch, M.</au><au>Greco, J.</au><au>Rascoe, J.</au><au>Ahlgren, D.</au><au>Joseph, A.</au><au>Dunn, J.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Collector optimization in advanced SiGe HBT technologies</atitle><btitle>IEEE Compound Semiconductor Integrated Circuit Symposium, 2005. CSIC '05</btitle><stitle>CSICS</stitle><date>2005</date><risdate>2005</risdate><spage>4 pp.</spage><pages>4 pp.-</pages><issn>1550-8781</issn><eissn>2374-8443</eissn><isbn>0780392507</isbn><isbn>9780780392502</isbn><abstract>With the advancement of the fT/fMAX performance scaling of SiGe HBTs the breakdown voltage (BVCBO/BVCEO) reduces commensurately, causing design related concerns. It is important, therefore, that multiple fT/BVCEO devices be offered in the RF technologies to meet the varying needs of the communication products. Unlike the GaAs technologies, the SiGe BiCMOS technologies are capable of integrating various flavors of fT/BVCEO SiGe HBT devices at a technology node. In this work, we investigate the tradeoff in fT-BVCEO for advanced SiGe HBTs by various collector optimization schemes such as, subcollector dopant species and concentration, epilayer thickness, SIC and other layout techniques.</abstract><pub>IEEE</pub><doi>10.1109/CSICS.2005.1531779</doi></addata></record> |
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| identifier | ISSN: 1550-8781 |
| ispartof | IEEE Compound Semiconductor Integrated Circuit Symposium, 2005. CSIC '05, 2005, p.4 pp. |
| issn | 1550-8781 2374-8443 |
| language | eng |
| recordid | cdi_ieee_primary_1531779 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | BiCMOS integrated circuits CMOS technology Delay Design optimization Doping Electric breakdown Germanium silicon alloys Heterojunction bipolar transistors Silicon carbide Silicon germanium |
| title | Collector optimization in advanced SiGe HBT technologies |
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