An acoustic echo canceller chip
This paper has mentioned new algorithms in adaptive acoustic echo cancellation (AEC): subband adaptive filtering (SAF) and partitioned block Hartley domain adaptive filtering (PBHDAF). The computational complexity of these algorithms is less than their older partners with very fast convergence rate....
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| creator | Borhani, M. Sedghi, V. |
| description | This paper has mentioned new algorithms in adaptive acoustic echo cancellation (AEC): subband adaptive filtering (SAF) and partitioned block Hartley domain adaptive filtering (PBHDAF). The computational complexity of these algorithms is less than their older partners with very fast convergence rate. We have proposed these algorithms for real time processing and we implement this system as acoustic echo canceller with very high speed integrated circuit hardware description language (VHDL). Also a block diagram for integrated implementation of this AEC is proposed that can be constructed in system on chip (SOC) or system in package (SIP) technologies. |
| doi_str_mv | 10.1109/IWSOC.2005.36 |
| format | Conference Proceeding |
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The computational complexity of these algorithms is less than their older partners with very fast convergence rate. We have proposed these algorithms for real time processing and we implement this system as acoustic echo canceller with very high speed integrated circuit hardware description language (VHDL). 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The computational complexity of these algorithms is less than their older partners with very fast convergence rate. We have proposed these algorithms for real time processing and we implement this system as acoustic echo canceller with very high speed integrated circuit hardware description language (VHDL). Also a block diagram for integrated implementation of this AEC is proposed that can be constructed in system on chip (SOC) or system in package (SIP) technologies.</description><subject>Adaptive filters</subject><subject>Computational complexity</subject><subject>Convergence</subject><subject>Echo cancellers</subject><subject>Filtering algorithms</subject><subject>Hardware design languages</subject><subject>Partitioning algorithms</subject><subject>Real time systems</subject><subject>System-on-a-chip</subject><subject>Very high speed integrated circuits</subject><isbn>9780769524030</isbn><isbn>0769524036</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2005</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotjk1Lw0AQQBdEUGqOnnowfyBxdqc7u3MswY9CoQcVj2UzO7GR2JakHvz3FvRd3u3xjLm1UFsLfL96f9k0tQPwNdKFKThECMTeLQDhyhTT9AlnkAkjX5u75b5McvieTr2UKrtDKWkvOgw6lrLrjzfmskvDpMW_Z-bt8eG1ea7Wm6dVs1xXH87SqcKQhaNvswZK4KRNscOsTNx2wi5addKptxAkucwduhTJUvZKqEQRZ2b-1-1VdXsc-680_mytR-Dz-C-fqzuA</recordid><startdate>2005</startdate><enddate>2005</enddate><creator>Borhani, M.</creator><creator>Sedghi, V.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>2005</creationdate><title>An acoustic echo canceller chip</title><author>Borhani, M. ; Sedghi, V.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-g216t-37dc985bde76a02cba8f3de969bfc9281e2cfe5107ca2d9f32a8616d5e63e6683</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2005</creationdate><topic>Adaptive filters</topic><topic>Computational complexity</topic><topic>Convergence</topic><topic>Echo cancellers</topic><topic>Filtering algorithms</topic><topic>Hardware design languages</topic><topic>Partitioning algorithms</topic><topic>Real time systems</topic><topic>System-on-a-chip</topic><topic>Very high speed integrated circuits</topic><toplevel>online_resources</toplevel><creatorcontrib>Borhani, M.</creatorcontrib><creatorcontrib>Sedghi, V.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Borhani, M.</au><au>Sedghi, V.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>An acoustic echo canceller chip</atitle><btitle>Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)</btitle><stitle>IWSOC</stitle><date>2005</date><risdate>2005</risdate><spage>193</spage><epage>198</epage><pages>193-198</pages><isbn>9780769524030</isbn><isbn>0769524036</isbn><abstract>This paper has mentioned new algorithms in adaptive acoustic echo cancellation (AEC): subband adaptive filtering (SAF) and partitioned block Hartley domain adaptive filtering (PBHDAF). The computational complexity of these algorithms is less than their older partners with very fast convergence rate. We have proposed these algorithms for real time processing and we implement this system as acoustic echo canceller with very high speed integrated circuit hardware description language (VHDL). Also a block diagram for integrated implementation of this AEC is proposed that can be constructed in system on chip (SOC) or system in package (SIP) technologies.</abstract><pub>IEEE</pub><doi>10.1109/IWSOC.2005.36</doi><tpages>6</tpages></addata></record> |
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| ispartof | Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05), 2005, p.193-198 |
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| language | eng |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Adaptive filters Computational complexity Convergence Echo cancellers Filtering algorithms Hardware design languages Partitioning algorithms Real time systems System-on-a-chip Very high speed integrated circuits |
| title | An acoustic echo canceller chip |
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