Application of evolutionary algorithm to three key problems in VLSI layout
Evolutionary algorithm is a class of stochastic search algorithm, which can be applied to both combinatorial and numerical optimization problems, especially NP hard problems. Circuit partitioning, placement and clock routing are three key phases in VLSI physical design and they are proved to be NP h...
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| creator | Guo-Fang Nan Min-Qiang Li Dan Lin Ji-Song Kou |
| description | Evolutionary algorithm is a class of stochastic search algorithm, which can be applied to both combinatorial and numerical optimization problems, especially NP hard problems. Circuit partitioning, placement and clock routing are three key phases in VLSI physical design and they are proved to be NP hard. So a genetic algorithm frame and its realization process are presented in this paper in order to solve these problems. Meanwhile, this algorithm is used to test different benchmarks for three different problems, experimental results show that it is a feasible and valid algorithm. This genetic algorithm can also improve solutions when compared with traditional heuristic methods. |
| doi_str_mv | 10.1109/ICMLC.2005.1527443 |
| format | Conference Proceeding |
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Circuit partitioning, placement and clock routing are three key phases in VLSI physical design and they are proved to be NP hard. So a genetic algorithm frame and its realization process are presented in this paper in order to solve these problems. Meanwhile, this algorithm is used to test different benchmarks for three different problems, experimental results show that it is a feasible and valid algorithm. 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Circuit partitioning, placement and clock routing are three key phases in VLSI physical design and they are proved to be NP hard. So a genetic algorithm frame and its realization process are presented in this paper in order to solve these problems. Meanwhile, this algorithm is used to test different benchmarks for three different problems, experimental results show that it is a feasible and valid algorithm. This genetic algorithm can also improve solutions when compared with traditional heuristic methods.</description><subject>Benchmark testing</subject><subject>Circuit testing</subject><subject>Clocks</subject><subject>Evolutionary algorithm</subject><subject>Evolutionary computation</subject><subject>genetic algorithm</subject><subject>Genetic algorithms</subject><subject>NP hard</subject><subject>NP-hard problem</subject><subject>Partitioning algorithms</subject><subject>physical design</subject><subject>Routing</subject><subject>Stochastic processes</subject><subject>Very large scale integration</subject><issn>2160-133X</issn><isbn>0780390911</isbn><isbn>9780780390911</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2005</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotj8tOwzAURC0BEqX0B2DjH0i5tuM4XlYRj6AgFjzErnL8oAanjhIXKX9PEJ3NaDZHcxC6IrAmBORNXT011ZoC8DXhVOQ5O0EXIEpgEiQhp2hBSQEZYezjHK3G8QvmMMkLBgv0uOn74LVKPu5xdNj-xHD4G2qYsAqfcfBp1-EUcdoN1uJvO-F-iG2w3Yj9Hr83LzUOaoqHdInOnAqjXR17id7ubl-rh6x5vq-rTZN5AjxluZWlFoa3QA1zmjujTM5AGiYKa3hOS-2o5K0p8pKWswIvtGRtqwUxXHDHluj6n-uttdt-8N38dXtUZ7_bIU2x</recordid><startdate>2005</startdate><enddate>2005</enddate><creator>Guo-Fang Nan</creator><creator>Min-Qiang Li</creator><creator>Dan Lin</creator><creator>Ji-Song Kou</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>2005</creationdate><title>Application of evolutionary algorithm to three key problems in VLSI layout</title><author>Guo-Fang Nan ; Min-Qiang Li ; Dan Lin ; Ji-Song Kou</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i105t-4e98c7d5b02d3fc5fdad4309d376ed5428cf295bd6482890956c93bbc71d575f3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2005</creationdate><topic>Benchmark testing</topic><topic>Circuit testing</topic><topic>Clocks</topic><topic>Evolutionary algorithm</topic><topic>Evolutionary computation</topic><topic>genetic algorithm</topic><topic>Genetic algorithms</topic><topic>NP hard</topic><topic>NP-hard problem</topic><topic>Partitioning algorithms</topic><topic>physical design</topic><topic>Routing</topic><topic>Stochastic processes</topic><topic>Very large scale integration</topic><toplevel>online_resources</toplevel><creatorcontrib>Guo-Fang Nan</creatorcontrib><creatorcontrib>Min-Qiang Li</creatorcontrib><creatorcontrib>Dan Lin</creatorcontrib><creatorcontrib>Ji-Song Kou</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Guo-Fang Nan</au><au>Min-Qiang Li</au><au>Dan Lin</au><au>Ji-Song Kou</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Application of evolutionary algorithm to three key problems in VLSI layout</atitle><btitle>2005 International Conference on Machine Learning and Cybernetics</btitle><stitle>ICMLC</stitle><date>2005</date><risdate>2005</risdate><volume>5</volume><spage>2929</spage><epage>2933 Vol. 5</epage><pages>2929-2933 Vol. 5</pages><issn>2160-133X</issn><isbn>0780390911</isbn><isbn>9780780390911</isbn><abstract>Evolutionary algorithm is a class of stochastic search algorithm, which can be applied to both combinatorial and numerical optimization problems, especially NP hard problems. Circuit partitioning, placement and clock routing are three key phases in VLSI physical design and they are proved to be NP hard. So a genetic algorithm frame and its realization process are presented in this paper in order to solve these problems. Meanwhile, this algorithm is used to test different benchmarks for three different problems, experimental results show that it is a feasible and valid algorithm. This genetic algorithm can also improve solutions when compared with traditional heuristic methods.</abstract><pub>IEEE</pub><doi>10.1109/ICMLC.2005.1527443</doi></addata></record> |
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| ispartof | 2005 International Conference on Machine Learning and Cybernetics, 2005, Vol.5, p.2929-2933 Vol. 5 |
| issn | 2160-133X |
| language | eng |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Benchmark testing Circuit testing Clocks Evolutionary algorithm Evolutionary computation genetic algorithm Genetic algorithms NP hard NP-hard problem Partitioning algorithms physical design Routing Stochastic processes Very large scale integration |
| title | Application of evolutionary algorithm to three key problems in VLSI layout |
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