A NUCA model for embedded systems cache design
Embedded applications require high performance processors integrating fast and low-power cache. Dynamic non-uniform cache architectures (D-NUCA) have been proposed to overcome the performance limit introduced by wire delays when designing large cache. In this paper, we propose alternative designs of...
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| creator | Foglia, P. Mangano, D. Prete, C.A. |
| description | Embedded applications require high performance processors integrating fast and low-power cache. Dynamic non-uniform cache architectures (D-NUCA) have been proposed to overcome the performance limit introduced by wire delays when designing large cache. In this paper, we propose alternative designs of D-NUCA cache, namely triangular D-NUCA cache, to reduce power consumption and silicon area occupancy of D-NUCA cache. We compare the performances of triangular D-NUCA cache with conventional rectangular organization. Results show that our approach is particular useful in the embedded applications domain, as it permits the utilization of half-sized NUCA cache with performance improvements. |
| doi_str_mv | 10.1109/ESTMED.2005.1518068 |
| format | Conference Proceeding |
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Dynamic non-uniform cache architectures (D-NUCA) have been proposed to overcome the performance limit introduced by wire delays when designing large cache. In this paper, we propose alternative designs of D-NUCA cache, namely triangular D-NUCA cache, to reduce power consumption and silicon area occupancy of D-NUCA cache. We compare the performances of triangular D-NUCA cache with conventional rectangular organization. Results show that our approach is particular useful in the embedded applications domain, as it permits the utilization of half-sized NUCA cache with performance improvements.</description><identifier>ISBN: 9780780393479</identifier><identifier>ISBN: 0780393473</identifier><identifier>DOI: 10.1109/ESTMED.2005.1518068</identifier><language>eng</language><publisher>IEEE</publisher><subject>Communication system security ; Computer applications ; Delay ; Embedded system ; Energy consumption ; Geometry ; Silicon ; Speech recognition ; Switches ; Wire</subject><ispartof>3rd Workshop on Embedded Systems for Real-Time Multimedia, 2005, 2005, p.41-46</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/1518068$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2056,4048,4049,27924,54919</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/1518068$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Foglia, P.</creatorcontrib><creatorcontrib>Mangano, D.</creatorcontrib><creatorcontrib>Prete, C.A.</creatorcontrib><title>A NUCA model for embedded systems cache design</title><title>3rd Workshop on Embedded Systems for Real-Time Multimedia, 2005</title><addtitle>ESTMED</addtitle><description>Embedded applications require high performance processors integrating fast and low-power cache. Dynamic non-uniform cache architectures (D-NUCA) have been proposed to overcome the performance limit introduced by wire delays when designing large cache. In this paper, we propose alternative designs of D-NUCA cache, namely triangular D-NUCA cache, to reduce power consumption and silicon area occupancy of D-NUCA cache. We compare the performances of triangular D-NUCA cache with conventional rectangular organization. Results show that our approach is particular useful in the embedded applications domain, as it permits the utilization of half-sized NUCA cache with performance improvements.</description><subject>Communication system security</subject><subject>Computer applications</subject><subject>Delay</subject><subject>Embedded system</subject><subject>Energy consumption</subject><subject>Geometry</subject><subject>Silicon</subject><subject>Speech recognition</subject><subject>Switches</subject><subject>Wire</subject><isbn>9780780393479</isbn><isbn>0780393473</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2005</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotj81uwjAQhC2hSlQ0T8DFL5DUG8c_e4zS9Eei5QCckfFuaBApVcyFt2-kMhppvtOMRoglqAJA4XO72X62L0WplCnAgFfWz0SGzqvJGnXlcC6ylE5qksbKevcoilp-7ZpaDhfis-wuo-ThwERMMt3SlYckY4jfLIlTf_x5Eg9dOCfO7rkQu9d227znq_XbR1Ov8h6cueZQkY7U-WgcwoTRatLKUmVL71QEf3ARrfVsQlcSTnNoDZEHQDSBg16I5X9vz8z737Efwnjb31_pP6VOQW0</recordid><startdate>2005</startdate><enddate>2005</enddate><creator>Foglia, P.</creator><creator>Mangano, D.</creator><creator>Prete, C.A.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>2005</creationdate><title>A NUCA model for embedded systems cache design</title><author>Foglia, P. ; Mangano, D. ; Prete, C.A.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-14d3cdf8c5791d3cc63d306d462870c18b7c9668e5af2d9dde965dd811995aea3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2005</creationdate><topic>Communication system security</topic><topic>Computer applications</topic><topic>Delay</topic><topic>Embedded system</topic><topic>Energy consumption</topic><topic>Geometry</topic><topic>Silicon</topic><topic>Speech recognition</topic><topic>Switches</topic><topic>Wire</topic><toplevel>online_resources</toplevel><creatorcontrib>Foglia, P.</creatorcontrib><creatorcontrib>Mangano, D.</creatorcontrib><creatorcontrib>Prete, C.A.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE/IET Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Foglia, P.</au><au>Mangano, D.</au><au>Prete, C.A.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A NUCA model for embedded systems cache design</atitle><btitle>3rd Workshop on Embedded Systems for Real-Time Multimedia, 2005</btitle><stitle>ESTMED</stitle><date>2005</date><risdate>2005</risdate><spage>41</spage><epage>46</epage><pages>41-46</pages><isbn>9780780393479</isbn><isbn>0780393473</isbn><abstract>Embedded applications require high performance processors integrating fast and low-power cache. Dynamic non-uniform cache architectures (D-NUCA) have been proposed to overcome the performance limit introduced by wire delays when designing large cache. In this paper, we propose alternative designs of D-NUCA cache, namely triangular D-NUCA cache, to reduce power consumption and silicon area occupancy of D-NUCA cache. We compare the performances of triangular D-NUCA cache with conventional rectangular organization. Results show that our approach is particular useful in the embedded applications domain, as it permits the utilization of half-sized NUCA cache with performance improvements.</abstract><pub>IEEE</pub><doi>10.1109/ESTMED.2005.1518068</doi><tpages>6</tpages></addata></record> |
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| ispartof | 3rd Workshop on Embedded Systems for Real-Time Multimedia, 2005, 2005, p.41-46 |
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| language | eng |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Communication system security Computer applications Delay Embedded system Energy consumption Geometry Silicon Speech recognition Switches Wire |
| title | A NUCA model for embedded systems cache design |
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