Parameterized logic power consumption models for FPGA-based arithmetic

The need for fast power estimation methods is a growing requirement in tools which perform power consumption optimization. This paper addresses the requirement by presenting a technique which is capable of providing a power estimate using only the word-level statistics of signals within an arithmeti...

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Bibliographische Detailangaben

Hauptverfasser:	Clarke, J.A., Gaffar, A.A., Constantinides, G.A.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Arithmetic Circuits Design optimization Energy consumption Field programmable gate arrays Hardware Logic Signal analysis Signal design Statistics
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