A new 40-nm SONOS structure based on backside trapping for nanoscale memories
Silicon-on-nothing (SON) devices have been analyzed for the first time in view of nanoscaled nonvolatile memories (NVM) applications. Two reliable steady states have been demonstrated using backside charge trapping in the nitride layer under the channel as a memory effect in a 40-nm gate-length pMOS...
Gespeichert in:
| Veröffentlicht in: | IEEE transactions on nanotechnology 2005-09, Vol.4 (5), p.581-587 |
|---|---|
| Hauptverfasser: | , , , , , , , , , |
| Format: | Artikel |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | 587 |
|---|---|
| container_issue | 5 |
| container_start_page | 581 |
| container_title | IEEE transactions on nanotechnology |
| container_volume | 4 |
| creator | Ranica, R. Villaret, A. Mazoyer, P. Monfray, S. Chanemougame, D. Masson, P. Regnier, A. Dray, C.N. Bez, R. Skotnicki, T. |
| description | Silicon-on-nothing (SON) devices have been analyzed for the first time in view of nanoscaled nonvolatile memories (NVM) applications. Two reliable steady states have been demonstrated using backside charge trapping in the nitride layer under the channel as a memory effect in a 40-nm gate-length pMOS silicon-oxide-nitride-oxide-silicon device realized with SON technology. Low voltages (/spl sim/3 V) are required for memory operations and a threshold voltage memory window superior to 0.5 V can be achieved. Charge loss mechanism is analyzed and very promising data retention behavior is demonstrated at 125/spl deg/C. This architecture, with a storage node localized under the channel, is exactly the same device that can operate as a high-performance transistor at low voltages and as an NVM cell at higher voltage ranges. A total compatibility between logic and the embedded NVM process is thus insured. In view of high-density memories, the feasibility of 2-bit storage in a longer SON device is also demonstrated. |
| doi_str_mv | 10.1109/TNANO.2005.851416 |
| format | Article |
| fullrecord | <record><control><sourceid>proquest_RIE</sourceid><recordid>TN_cdi_ieee_primary_1504717</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>1504717</ieee_id><sourcerecordid>28040230</sourcerecordid><originalsourceid>FETCH-LOGICAL-c482t-5e71edb5688b4ae739f0701cb6d5e66fffe7c52bfb878670fc50d00286b9bd9d3</originalsourceid><addsrcrecordid>eNqNkU-L1EAQxYMouK5-APHSCLqnjFWd_nscFnWFdeawK3hrOp1qyTrpjN0J4rc3cRYWPIinelC_elTVq6qXCBtEsO9ud9vdfsMB5MZIFKgeVWdoBdYARj5etGxUjVx-fVo9K-UOALWS5qz6vGWJfjIBdRrYzX63v2FlynOY5kys9YU6NqZFhO-l74hN2R-PffrG4phZ8mkswR-IDTSMuafyvHoS_aHQi_t6Xn358P728qq-3n_8dLm9roMwfKolaaSulcqYVnjSjY2gAUOrOklKxRhJB8nb2BptlIYYJHQA3KjWtp3tmvPq4uR7zOOPmcrkhr4EOhx8onEuzljFkRsBC_n2nyQ3KJRSzX-AIIA3q-Prv8C7cc5pOddZ5KAtR7FAeIJCHkvJFN0x94PPvxyCWwNzfwJza2DuFNgy8-be2K9fjdmn0JeHQY2IjV03fXXieiJ6aEsQGnXzG_e6nMw</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>912079214</pqid></control><display><type>article</type><title>A new 40-nm SONOS structure based on backside trapping for nanoscale memories</title><source>IEEE Electronic Library (IEL)</source><creator>Ranica, R. ; Villaret, A. ; Mazoyer, P. ; Monfray, S. ; Chanemougame, D. ; Masson, P. ; Regnier, A. ; Dray, C.N. ; Bez, R. ; Skotnicki, T.</creator><creatorcontrib>Ranica, R. ; Villaret, A. ; Mazoyer, P. ; Monfray, S. ; Chanemougame, D. ; Masson, P. ; Regnier, A. ; Dray, C.N. ; Bez, R. ; Skotnicki, T.</creatorcontrib><description>Silicon-on-nothing (SON) devices have been analyzed for the first time in view of nanoscaled nonvolatile memories (NVM) applications. Two reliable steady states have been demonstrated using backside charge trapping in the nitride layer under the channel as a memory effect in a 40-nm gate-length pMOS silicon-oxide-nitride-oxide-silicon device realized with SON technology. Low voltages (/spl sim/3 V) are required for memory operations and a threshold voltage memory window superior to 0.5 V can be achieved. Charge loss mechanism is analyzed and very promising data retention behavior is demonstrated at 125/spl deg/C. This architecture, with a storage node localized under the channel, is exactly the same device that can operate as a high-performance transistor at low voltages and as an NVM cell at higher voltage ranges. A total compatibility between logic and the embedded NVM process is thus insured. In view of high-density memories, the feasibility of 2-bit storage in a longer SON device is also demonstrated.</description><identifier>ISSN: 1536-125X</identifier><identifier>EISSN: 1941-0085</identifier><identifier>DOI: 10.1109/TNANO.2005.851416</identifier><identifier>CODEN: ITNECU</identifier><language>eng</language><publisher>New York, NY: IEEE</publisher><subject>Applied sciences ; Channels ; Charge ; Charge trapping ; CMOS integrated memories ; CMOS logic circuits ; Devices ; Electronics ; Exact sciences and technology ; Integrated circuits ; Integrated circuits by function (including memories and processors) ; Logic arrays ; Logic devices ; Low voltage ; Molecular electronics, nanoelectronics ; Nanocomposites ; Nanomaterials ; Nanoscale devices ; Nanostructure ; nitride traps ; nonvolatile memories (NVMs) ; Nonvolatile memory ; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices ; silicon-oxide-nitride-oxide-silicon (SONOS) memory ; SONOS devices ; Steady-state ; Threshold voltage ; Trapping</subject><ispartof>IEEE transactions on nanotechnology, 2005-09, Vol.4 (5), p.581-587</ispartof><rights>2005 INIST-CNRS</rights><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2005</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c482t-5e71edb5688b4ae739f0701cb6d5e66fffe7c52bfb878670fc50d00286b9bd9d3</citedby><cites>FETCH-LOGICAL-c482t-5e71edb5688b4ae739f0701cb6d5e66fffe7c52bfb878670fc50d00286b9bd9d3</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/1504717$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,796,27923,27924,54757</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/1504717$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=17111393$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><creatorcontrib>Ranica, R.</creatorcontrib><creatorcontrib>Villaret, A.</creatorcontrib><creatorcontrib>Mazoyer, P.</creatorcontrib><creatorcontrib>Monfray, S.</creatorcontrib><creatorcontrib>Chanemougame, D.</creatorcontrib><creatorcontrib>Masson, P.</creatorcontrib><creatorcontrib>Regnier, A.</creatorcontrib><creatorcontrib>Dray, C.N.</creatorcontrib><creatorcontrib>Bez, R.</creatorcontrib><creatorcontrib>Skotnicki, T.</creatorcontrib><title>A new 40-nm SONOS structure based on backside trapping for nanoscale memories</title><title>IEEE transactions on nanotechnology</title><addtitle>TNANO</addtitle><description>Silicon-on-nothing (SON) devices have been analyzed for the first time in view of nanoscaled nonvolatile memories (NVM) applications. Two reliable steady states have been demonstrated using backside charge trapping in the nitride layer under the channel as a memory effect in a 40-nm gate-length pMOS silicon-oxide-nitride-oxide-silicon device realized with SON technology. Low voltages (/spl sim/3 V) are required for memory operations and a threshold voltage memory window superior to 0.5 V can be achieved. Charge loss mechanism is analyzed and very promising data retention behavior is demonstrated at 125/spl deg/C. This architecture, with a storage node localized under the channel, is exactly the same device that can operate as a high-performance transistor at low voltages and as an NVM cell at higher voltage ranges. A total compatibility between logic and the embedded NVM process is thus insured. In view of high-density memories, the feasibility of 2-bit storage in a longer SON device is also demonstrated.</description><subject>Applied sciences</subject><subject>Channels</subject><subject>Charge</subject><subject>Charge trapping</subject><subject>CMOS integrated memories</subject><subject>CMOS logic circuits</subject><subject>Devices</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>Integrated circuits</subject><subject>Integrated circuits by function (including memories and processors)</subject><subject>Logic arrays</subject><subject>Logic devices</subject><subject>Low voltage</subject><subject>Molecular electronics, nanoelectronics</subject><subject>Nanocomposites</subject><subject>Nanomaterials</subject><subject>Nanoscale devices</subject><subject>Nanostructure</subject><subject>nitride traps</subject><subject>nonvolatile memories (NVMs)</subject><subject>Nonvolatile memory</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><subject>silicon-oxide-nitride-oxide-silicon (SONOS) memory</subject><subject>SONOS devices</subject><subject>Steady-state</subject><subject>Threshold voltage</subject><subject>Trapping</subject><issn>1536-125X</issn><issn>1941-0085</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2005</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNqNkU-L1EAQxYMouK5-APHSCLqnjFWd_nscFnWFdeawK3hrOp1qyTrpjN0J4rc3cRYWPIinelC_elTVq6qXCBtEsO9ud9vdfsMB5MZIFKgeVWdoBdYARj5etGxUjVx-fVo9K-UOALWS5qz6vGWJfjIBdRrYzX63v2FlynOY5kys9YU6NqZFhO-l74hN2R-PffrG4phZ8mkswR-IDTSMuafyvHoS_aHQi_t6Xn358P728qq-3n_8dLm9roMwfKolaaSulcqYVnjSjY2gAUOrOklKxRhJB8nb2BptlIYYJHQA3KjWtp3tmvPq4uR7zOOPmcrkhr4EOhx8onEuzljFkRsBC_n2nyQ3KJRSzX-AIIA3q-Prv8C7cc5pOddZ5KAtR7FAeIJCHkvJFN0x94PPvxyCWwNzfwJza2DuFNgy8-be2K9fjdmn0JeHQY2IjV03fXXieiJ6aEsQGnXzG_e6nMw</recordid><startdate>20050901</startdate><enddate>20050901</enddate><creator>Ranica, R.</creator><creator>Villaret, A.</creator><creator>Mazoyer, P.</creator><creator>Monfray, S.</creator><creator>Chanemougame, D.</creator><creator>Masson, P.</creator><creator>Regnier, A.</creator><creator>Dray, C.N.</creator><creator>Bez, R.</creator><creator>Skotnicki, T.</creator><general>IEEE</general><general>Institute of Electrical and Electronics Engineers</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>IQODW</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>7SR</scope><scope>7U5</scope><scope>8BQ</scope><scope>8FD</scope><scope>JG9</scope><scope>L7M</scope><scope>F28</scope><scope>FR3</scope></search><sort><creationdate>20050901</creationdate><title>A new 40-nm SONOS structure based on backside trapping for nanoscale memories</title><author>Ranica, R. ; Villaret, A. ; Mazoyer, P. ; Monfray, S. ; Chanemougame, D. ; Masson, P. ; Regnier, A. ; Dray, C.N. ; Bez, R. ; Skotnicki, T.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c482t-5e71edb5688b4ae739f0701cb6d5e66fffe7c52bfb878670fc50d00286b9bd9d3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2005</creationdate><topic>Applied sciences</topic><topic>Channels</topic><topic>Charge</topic><topic>Charge trapping</topic><topic>CMOS integrated memories</topic><topic>CMOS logic circuits</topic><topic>Devices</topic><topic>Electronics</topic><topic>Exact sciences and technology</topic><topic>Integrated circuits</topic><topic>Integrated circuits by function (including memories and processors)</topic><topic>Logic arrays</topic><topic>Logic devices</topic><topic>Low voltage</topic><topic>Molecular electronics, nanoelectronics</topic><topic>Nanocomposites</topic><topic>Nanomaterials</topic><topic>Nanoscale devices</topic><topic>Nanostructure</topic><topic>nitride traps</topic><topic>nonvolatile memories (NVMs)</topic><topic>Nonvolatile memory</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</topic><topic>silicon-oxide-nitride-oxide-silicon (SONOS) memory</topic><topic>SONOS devices</topic><topic>Steady-state</topic><topic>Threshold voltage</topic><topic>Trapping</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Ranica, R.</creatorcontrib><creatorcontrib>Villaret, A.</creatorcontrib><creatorcontrib>Mazoyer, P.</creatorcontrib><creatorcontrib>Monfray, S.</creatorcontrib><creatorcontrib>Chanemougame, D.</creatorcontrib><creatorcontrib>Masson, P.</creatorcontrib><creatorcontrib>Regnier, A.</creatorcontrib><creatorcontrib>Dray, C.N.</creatorcontrib><creatorcontrib>Bez, R.</creatorcontrib><creatorcontrib>Skotnicki, T.</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Engineered Materials Abstracts</collection><collection>Solid State and Superconductivity Abstracts</collection><collection>METADEX</collection><collection>Technology Research Database</collection><collection>Materials Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>ANTE: Abstracts in New Technology & Engineering</collection><collection>Engineering Research Database</collection><jtitle>IEEE transactions on nanotechnology</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Ranica, R.</au><au>Villaret, A.</au><au>Mazoyer, P.</au><au>Monfray, S.</au><au>Chanemougame, D.</au><au>Masson, P.</au><au>Regnier, A.</au><au>Dray, C.N.</au><au>Bez, R.</au><au>Skotnicki, T.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>A new 40-nm SONOS structure based on backside trapping for nanoscale memories</atitle><jtitle>IEEE transactions on nanotechnology</jtitle><stitle>TNANO</stitle><date>2005-09-01</date><risdate>2005</risdate><volume>4</volume><issue>5</issue><spage>581</spage><epage>587</epage><pages>581-587</pages><issn>1536-125X</issn><eissn>1941-0085</eissn><coden>ITNECU</coden><abstract>Silicon-on-nothing (SON) devices have been analyzed for the first time in view of nanoscaled nonvolatile memories (NVM) applications. Two reliable steady states have been demonstrated using backside charge trapping in the nitride layer under the channel as a memory effect in a 40-nm gate-length pMOS silicon-oxide-nitride-oxide-silicon device realized with SON technology. Low voltages (/spl sim/3 V) are required for memory operations and a threshold voltage memory window superior to 0.5 V can be achieved. Charge loss mechanism is analyzed and very promising data retention behavior is demonstrated at 125/spl deg/C. This architecture, with a storage node localized under the channel, is exactly the same device that can operate as a high-performance transistor at low voltages and as an NVM cell at higher voltage ranges. A total compatibility between logic and the embedded NVM process is thus insured. In view of high-density memories, the feasibility of 2-bit storage in a longer SON device is also demonstrated.</abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/TNANO.2005.851416</doi><tpages>7</tpages></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 1536-125X |
| ispartof | IEEE transactions on nanotechnology, 2005-09, Vol.4 (5), p.581-587 |
| issn | 1536-125X 1941-0085 |
| language | eng |
| recordid | cdi_ieee_primary_1504717 |
| source | IEEE Electronic Library (IEL) |
| subjects | Applied sciences Channels Charge Charge trapping CMOS integrated memories CMOS logic circuits Devices Electronics Exact sciences and technology Integrated circuits Integrated circuits by function (including memories and processors) Logic arrays Logic devices Low voltage Molecular electronics, nanoelectronics Nanocomposites Nanomaterials Nanoscale devices Nanostructure nitride traps nonvolatile memories (NVMs) Nonvolatile memory Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices silicon-oxide-nitride-oxide-silicon (SONOS) memory SONOS devices Steady-state Threshold voltage Trapping |
| title | A new 40-nm SONOS structure based on backside trapping for nanoscale memories |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-11T14%3A10%3A21IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_RIE&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=A%20new%2040-nm%20SONOS%20structure%20based%20on%20backside%20trapping%20for%20nanoscale%20memories&rft.jtitle=IEEE%20transactions%20on%20nanotechnology&rft.au=Ranica,%20R.&rft.date=2005-09-01&rft.volume=4&rft.issue=5&rft.spage=581&rft.epage=587&rft.pages=581-587&rft.issn=1536-125X&rft.eissn=1941-0085&rft.coden=ITNECU&rft_id=info:doi/10.1109/TNANO.2005.851416&rft_dat=%3Cproquest_RIE%3E28040230%3C/proquest_RIE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=912079214&rft_id=info:pmid/&rft_ieee_id=1504717&rfr_iscdi=true |