A 4.8-6.4-Gb/s serial link for backplane applications using decision feedback equalization
In this paper, a serial link design that is capable of 4.8-6.4-Gb/s binary NRZ signaling across 40'' of FR4 copper backplane traces and two connectors is described. The transmitter features a programmable two-tap feed forward equalizer and the receiver uses an adaptive four-tap decision fe...
Gespeichert in:
| Veröffentlicht in: | IEEE journal of solid-state circuits 2005-09, Vol.40 (9), p.1957-1967 |
|---|---|
| Hauptverfasser: | , , , , , , , , , , , , , , , , |
| Format: | Artikel |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | 1967 |
|---|---|
| container_issue | 9 |
| container_start_page | 1957 |
| container_title | IEEE journal of solid-state circuits |
| container_volume | 40 |
| creator | Balan, V. Caroselli, J. Chern, J.-G. Chow, C. Dadi, R. Desai, C. Fang, L. Hsu, D. Joshi, P. Kimura, H. Liu, C.Y. Tzu-Wang Pan Park, R. You, C. Yi Zeng Zhang, E. Zhong, F. |
| description | In this paper, a serial link design that is capable of 4.8-6.4-Gb/s binary NRZ signaling across 40'' of FR4 copper backplane traces and two connectors is described. The transmitter features a programmable two-tap feed forward equalizer and the receiver uses an adaptive four-tap decision feedback equalization to compensate for the losses in the channel at 6.4 Gbps. The transceiver core is built in LSI's 0.13-/spl mu/m standard CMOS technology to be integrated into ASIC designs that require serial links. The transceiver consumes 310 mW per duplex channel at 1.2 V and 6.4 Gb/s under nominal conditions. |
| doi_str_mv | 10.1109/JSSC.2005.848180 |
| format | Article |
| fullrecord | <record><control><sourceid>proquest_RIE</sourceid><recordid>TN_cdi_ieee_primary_1501996</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>1501996</ieee_id><sourcerecordid>1671249465</sourcerecordid><originalsourceid>FETCH-LOGICAL-c415t-3ad844041a6bd506847375781f467a5a70e44f6b7aac01bab3797743ea3ffc753</originalsourceid><addsrcrecordid>eNqFkUFr3DAQhUVIIJtt74VeRCGlFzuatWRJx7A025RADkmg9CLGWqlo49iOtD6kvz5ydmGhh3QuwzDfPM3oEfIJWAnA9MXPu7tluWBMlIorUOyIzEAIVYCsfh2TGWOgCp37p-QspU0uecZm5Pcl5aUq6pIXq-Yi0eRiwJa2oXukvo-0Qfs4tNg5isPQBovb0HeJjil0f-ja2ZByTb1z64mk7nnENvx9oz6QE49tch_3eU4err7fL38UN7er6-XlTWE5iG1R4Vpxzjhg3awFqxWXlRRSgee1RIGSOc593UhEy6DBppJaSl45rLy3UlRz8nWnO8T-eXRpa55Csq6dtu7HZBYKFlww-D8otVKynhS_vQtCLbOk5m_ol3_QTT_GLt9rNCwY5NAZYjvIxj6l6LwZYnjC-GKAmck9M7lnJvfMzr08cr7XxWSx9RG7_NeHubyA0Gx6__OOC865Qzufq3VdvQKwM5_t</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>912011119</pqid></control><display><type>article</type><title>A 4.8-6.4-Gb/s serial link for backplane applications using decision feedback equalization</title><source>IEEE Electronic Library (IEL)</source><creator>Balan, V. ; Caroselli, J. ; Chern, J.-G. ; Chow, C. ; Dadi, R. ; Desai, C. ; Fang, L. ; Hsu, D. ; Joshi, P. ; Kimura, H. ; Liu, C.Y. ; Tzu-Wang Pan ; Park, R. ; You, C. ; Yi Zeng ; Zhang, E. ; Zhong, F.</creator><creatorcontrib>Balan, V. ; Caroselli, J. ; Chern, J.-G. ; Chow, C. ; Dadi, R. ; Desai, C. ; Fang, L. ; Hsu, D. ; Joshi, P. ; Kimura, H. ; Liu, C.Y. ; Tzu-Wang Pan ; Park, R. ; You, C. ; Yi Zeng ; Zhang, E. ; Zhong, F.</creatorcontrib><description>In this paper, a serial link design that is capable of 4.8-6.4-Gb/s binary NRZ signaling across 40'' of FR4 copper backplane traces and two connectors is described. The transmitter features a programmable two-tap feed forward equalizer and the receiver uses an adaptive four-tap decision feedback equalization to compensate for the losses in the channel at 6.4 Gbps. The transceiver core is built in LSI's 0.13-/spl mu/m standard CMOS technology to be integrated into ASIC designs that require serial links. The transceiver consumes 310 mW per duplex channel at 1.2 V and 6.4 Gb/s under nominal conditions.</description><identifier>ISSN: 0018-9200</identifier><identifier>EISSN: 1558-173X</identifier><identifier>DOI: 10.1109/JSSC.2005.848180</identifier><identifier>CODEN: IJSCBC</identifier><language>eng</language><publisher>New York, NY: IEEE</publisher><subject>Adaptive equalization ; Applied sciences ; backplane transceiver ; Backplanes ; Channels ; CMOS technology ; Connectors ; Copper ; decision feedback equalization (DFE) ; Decision feedback equalizers ; Design. Technologies. Operation analysis. Testing ; Electronic equipment and fabrication. Passive components, printed wiring boards, connectics ; Electronics ; Equalization ; Exact sciences and technology ; Feedback ; Feeds ; Integrated circuits ; Links ; Optical signal processing ; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices ; SerDes ; serial link ; Serials ; Signal design ; Transceivers ; Transmitters</subject><ispartof>IEEE journal of solid-state circuits, 2005-09, Vol.40 (9), p.1957-1967</ispartof><rights>2005 INIST-CNRS</rights><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2005</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c415t-3ad844041a6bd506847375781f467a5a70e44f6b7aac01bab3797743ea3ffc753</citedby><cites>FETCH-LOGICAL-c415t-3ad844041a6bd506847375781f467a5a70e44f6b7aac01bab3797743ea3ffc753</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/1501996$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>310,311,315,781,785,790,791,797,23932,23933,25142,27926,27927,54760</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/1501996$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=17125905$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><creatorcontrib>Balan, V.</creatorcontrib><creatorcontrib>Caroselli, J.</creatorcontrib><creatorcontrib>Chern, J.-G.</creatorcontrib><creatorcontrib>Chow, C.</creatorcontrib><creatorcontrib>Dadi, R.</creatorcontrib><creatorcontrib>Desai, C.</creatorcontrib><creatorcontrib>Fang, L.</creatorcontrib><creatorcontrib>Hsu, D.</creatorcontrib><creatorcontrib>Joshi, P.</creatorcontrib><creatorcontrib>Kimura, H.</creatorcontrib><creatorcontrib>Liu, C.Y.</creatorcontrib><creatorcontrib>Tzu-Wang Pan</creatorcontrib><creatorcontrib>Park, R.</creatorcontrib><creatorcontrib>You, C.</creatorcontrib><creatorcontrib>Yi Zeng</creatorcontrib><creatorcontrib>Zhang, E.</creatorcontrib><creatorcontrib>Zhong, F.</creatorcontrib><title>A 4.8-6.4-Gb/s serial link for backplane applications using decision feedback equalization</title><title>IEEE journal of solid-state circuits</title><addtitle>JSSC</addtitle><description>In this paper, a serial link design that is capable of 4.8-6.4-Gb/s binary NRZ signaling across 40'' of FR4 copper backplane traces and two connectors is described. The transmitter features a programmable two-tap feed forward equalizer and the receiver uses an adaptive four-tap decision feedback equalization to compensate for the losses in the channel at 6.4 Gbps. The transceiver core is built in LSI's 0.13-/spl mu/m standard CMOS technology to be integrated into ASIC designs that require serial links. The transceiver consumes 310 mW per duplex channel at 1.2 V and 6.4 Gb/s under nominal conditions.</description><subject>Adaptive equalization</subject><subject>Applied sciences</subject><subject>backplane transceiver</subject><subject>Backplanes</subject><subject>Channels</subject><subject>CMOS technology</subject><subject>Connectors</subject><subject>Copper</subject><subject>decision feedback equalization (DFE)</subject><subject>Decision feedback equalizers</subject><subject>Design. Technologies. Operation analysis. Testing</subject><subject>Electronic equipment and fabrication. Passive components, printed wiring boards, connectics</subject><subject>Electronics</subject><subject>Equalization</subject><subject>Exact sciences and technology</subject><subject>Feedback</subject><subject>Feeds</subject><subject>Integrated circuits</subject><subject>Links</subject><subject>Optical signal processing</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><subject>SerDes</subject><subject>serial link</subject><subject>Serials</subject><subject>Signal design</subject><subject>Transceivers</subject><subject>Transmitters</subject><issn>0018-9200</issn><issn>1558-173X</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2005</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNqFkUFr3DAQhUVIIJtt74VeRCGlFzuatWRJx7A025RADkmg9CLGWqlo49iOtD6kvz5ydmGhh3QuwzDfPM3oEfIJWAnA9MXPu7tluWBMlIorUOyIzEAIVYCsfh2TGWOgCp37p-QspU0uecZm5Pcl5aUq6pIXq-Yi0eRiwJa2oXukvo-0Qfs4tNg5isPQBovb0HeJjil0f-ja2ZByTb1z64mk7nnENvx9oz6QE49tch_3eU4err7fL38UN7er6-XlTWE5iG1R4Vpxzjhg3awFqxWXlRRSgee1RIGSOc593UhEy6DBppJaSl45rLy3UlRz8nWnO8T-eXRpa55Csq6dtu7HZBYKFlww-D8otVKynhS_vQtCLbOk5m_ol3_QTT_GLt9rNCwY5NAZYjvIxj6l6LwZYnjC-GKAmck9M7lnJvfMzr08cr7XxWSx9RG7_NeHubyA0Gx6__OOC865Qzufq3VdvQKwM5_t</recordid><startdate>20050901</startdate><enddate>20050901</enddate><creator>Balan, V.</creator><creator>Caroselli, J.</creator><creator>Chern, J.-G.</creator><creator>Chow, C.</creator><creator>Dadi, R.</creator><creator>Desai, C.</creator><creator>Fang, L.</creator><creator>Hsu, D.</creator><creator>Joshi, P.</creator><creator>Kimura, H.</creator><creator>Liu, C.Y.</creator><creator>Tzu-Wang Pan</creator><creator>Park, R.</creator><creator>You, C.</creator><creator>Yi Zeng</creator><creator>Zhang, E.</creator><creator>Zhong, F.</creator><general>IEEE</general><general>Institute of Electrical and Electronics Engineers</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>IQODW</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><scope>F28</scope><scope>FR3</scope><scope>KR7</scope><scope>8BQ</scope><scope>JG9</scope></search><sort><creationdate>20050901</creationdate><title>A 4.8-6.4-Gb/s serial link for backplane applications using decision feedback equalization</title><author>Balan, V. ; Caroselli, J. ; Chern, J.-G. ; Chow, C. ; Dadi, R. ; Desai, C. ; Fang, L. ; Hsu, D. ; Joshi, P. ; Kimura, H. ; Liu, C.Y. ; Tzu-Wang Pan ; Park, R. ; You, C. ; Yi Zeng ; Zhang, E. ; Zhong, F.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c415t-3ad844041a6bd506847375781f467a5a70e44f6b7aac01bab3797743ea3ffc753</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2005</creationdate><topic>Adaptive equalization</topic><topic>Applied sciences</topic><topic>backplane transceiver</topic><topic>Backplanes</topic><topic>Channels</topic><topic>CMOS technology</topic><topic>Connectors</topic><topic>Copper</topic><topic>decision feedback equalization (DFE)</topic><topic>Decision feedback equalizers</topic><topic>Design. Technologies. Operation analysis. Testing</topic><topic>Electronic equipment and fabrication. Passive components, printed wiring boards, connectics</topic><topic>Electronics</topic><topic>Equalization</topic><topic>Exact sciences and technology</topic><topic>Feedback</topic><topic>Feeds</topic><topic>Integrated circuits</topic><topic>Links</topic><topic>Optical signal processing</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</topic><topic>SerDes</topic><topic>serial link</topic><topic>Serials</topic><topic>Signal design</topic><topic>Transceivers</topic><topic>Transmitters</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Balan, V.</creatorcontrib><creatorcontrib>Caroselli, J.</creatorcontrib><creatorcontrib>Chern, J.-G.</creatorcontrib><creatorcontrib>Chow, C.</creatorcontrib><creatorcontrib>Dadi, R.</creatorcontrib><creatorcontrib>Desai, C.</creatorcontrib><creatorcontrib>Fang, L.</creatorcontrib><creatorcontrib>Hsu, D.</creatorcontrib><creatorcontrib>Joshi, P.</creatorcontrib><creatorcontrib>Kimura, H.</creatorcontrib><creatorcontrib>Liu, C.Y.</creatorcontrib><creatorcontrib>Tzu-Wang Pan</creatorcontrib><creatorcontrib>Park, R.</creatorcontrib><creatorcontrib>You, C.</creatorcontrib><creatorcontrib>Yi Zeng</creatorcontrib><creatorcontrib>Zhang, E.</creatorcontrib><creatorcontrib>Zhong, F.</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>ANTE: Abstracts in New Technology & Engineering</collection><collection>Engineering Research Database</collection><collection>Civil Engineering Abstracts</collection><collection>METADEX</collection><collection>Materials Research Database</collection><jtitle>IEEE journal of solid-state circuits</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Balan, V.</au><au>Caroselli, J.</au><au>Chern, J.-G.</au><au>Chow, C.</au><au>Dadi, R.</au><au>Desai, C.</au><au>Fang, L.</au><au>Hsu, D.</au><au>Joshi, P.</au><au>Kimura, H.</au><au>Liu, C.Y.</au><au>Tzu-Wang Pan</au><au>Park, R.</au><au>You, C.</au><au>Yi Zeng</au><au>Zhang, E.</au><au>Zhong, F.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>A 4.8-6.4-Gb/s serial link for backplane applications using decision feedback equalization</atitle><jtitle>IEEE journal of solid-state circuits</jtitle><stitle>JSSC</stitle><date>2005-09-01</date><risdate>2005</risdate><volume>40</volume><issue>9</issue><spage>1957</spage><epage>1967</epage><pages>1957-1967</pages><issn>0018-9200</issn><eissn>1558-173X</eissn><coden>IJSCBC</coden><abstract>In this paper, a serial link design that is capable of 4.8-6.4-Gb/s binary NRZ signaling across 40'' of FR4 copper backplane traces and two connectors is described. The transmitter features a programmable two-tap feed forward equalizer and the receiver uses an adaptive four-tap decision feedback equalization to compensate for the losses in the channel at 6.4 Gbps. The transceiver core is built in LSI's 0.13-/spl mu/m standard CMOS technology to be integrated into ASIC designs that require serial links. The transceiver consumes 310 mW per duplex channel at 1.2 V and 6.4 Gb/s under nominal conditions.</abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/JSSC.2005.848180</doi><tpages>11</tpages></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 0018-9200 |
| ispartof | IEEE journal of solid-state circuits, 2005-09, Vol.40 (9), p.1957-1967 |
| issn | 0018-9200 1558-173X |
| language | eng |
| recordid | cdi_ieee_primary_1501996 |
| source | IEEE Electronic Library (IEL) |
| subjects | Adaptive equalization Applied sciences backplane transceiver Backplanes Channels CMOS technology Connectors Copper decision feedback equalization (DFE) Decision feedback equalizers Design. Technologies. Operation analysis. Testing Electronic equipment and fabrication. Passive components, printed wiring boards, connectics Electronics Equalization Exact sciences and technology Feedback Feeds Integrated circuits Links Optical signal processing Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices SerDes serial link Serials Signal design Transceivers Transmitters |
| title | A 4.8-6.4-Gb/s serial link for backplane applications using decision feedback equalization |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-18T09%3A56%3A47IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_RIE&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=A%204.8-6.4-Gb/s%20serial%20link%20for%20backplane%20applications%20using%20decision%20feedback%20equalization&rft.jtitle=IEEE%20journal%20of%20solid-state%20circuits&rft.au=Balan,%20V.&rft.date=2005-09-01&rft.volume=40&rft.issue=9&rft.spage=1957&rft.epage=1967&rft.pages=1957-1967&rft.issn=0018-9200&rft.eissn=1558-173X&rft.coden=IJSCBC&rft_id=info:doi/10.1109/JSSC.2005.848180&rft_dat=%3Cproquest_RIE%3E1671249465%3C/proquest_RIE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=912011119&rft_id=info:pmid/&rft_ieee_id=1501996&rfr_iscdi=true |