Dual-tree error compensation for high performance fixed-width multipliers
In this paper, a new error-compensation network for fixed-width multipliers is proposed. The error-compensation block is composed of two summation trees which are optimally chosen in order to minimize either the mean-square error or the maximum absolute error. The new technique substantially improve...
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| Veröffentlicht in: | IEEE transactions on circuits and systems. 2, Analog and digital signal processing Analog and digital signal processing, 2005-08, Vol.52 (8), p.501-507 |
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| container_end_page | 507 |
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| container_title | IEEE transactions on circuits and systems. 2, Analog and digital signal processing |
| container_volume | 52 |
| creator | Strollo, A.G.M. Petra, N. De Caro, D. |
| description | In this paper, a new error-compensation network for fixed-width multipliers is proposed. The error-compensation block is composed of two summation trees which are optimally chosen in order to minimize either the mean-square error or the maximum absolute error. The new technique substantially improves error performances with respect to previously proposed approaches. Simulation results show that new fixed-width multipliers exhibit significant improvements both in propagation delay and in power dissipation with respect to previous solutions. |
| doi_str_mv | 10.1109/TCSII.2005.848979 |
| format | Article |
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| identifier | ISSN: 1549-7747 |
| ispartof | IEEE transactions on circuits and systems. 2, Analog and digital signal processing, 2005-08, Vol.52 (8), p.501-507 |
| issn | 1549-7747 1057-7130 1558-3791 |
| language | eng |
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| source | IEEE Electronic Library (IEL) |
| subjects | Circuit simulation Computer architecture Digital arithmetic Digital integrated circuits Digital signal processing Error compensation fixed-width multipliers Hardware multipliers Power dissipation Propagation delay Signal processing algorithms |
| title | Dual-tree error compensation for high performance fixed-width multipliers |
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