A chip-package hybrid DLL loop and clock distribution network for low-jitter clock delivery

A chip-package hybrid DLL loop and clock distribution network for low-jitter clock delivery

A chip-package hybrid DLL and clock distribution network provides low-jitter clock signals by utilizing separate supply connections and lossless package layer interconnections instead of on-chip global wires. The hybrid scheme has 78ps/sub co/ jitter and under 240mV digital noise at 500MHz, while a...

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Hauptverfasser: Daehyun Chung, Chunghyun Ryu, Hyungsoo Kim, Choonheung Lee, Jaedong Kim, Jinyoung Kim, Kicheol Bae, Jiheon Yu, Seungjae Lee, Hoijun Yoo, Kim, Joungho
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Circuit noise
Clocks
CMOS technology
Delay
Integrated circuit interconnections
Jitter
Noise generators
Packaging
Repeaters
Silicon
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Beschreibung
Zusammenfassung:A chip-package hybrid DLL and clock distribution network provides low-jitter clock signals by utilizing separate supply connections and lossless package layer interconnections instead of on-chip global wires. The hybrid scheme has 78ps/sub co/ jitter and under 240mV digital noise at 500MHz, while a conventional scheme has a 172ps/sub p-p/ jitter under the same conditions.
ISSN:0193-6530
2376-8606
DOI:10.1109/ISSCC.2005.1494095