An automated BIST approach for general sequential logic synthesis
An automated built-in self-test (BIST) technique for general sequential logic is described. This approach has been incorporated in a behavioral model synthesis system, providing automated implementation of BIST in very-large-scale-integration (VLSI) devices as well as programmable-logic-device (PLD)...
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| creator | Stroud, C.E. |
| description | An automated built-in self-test (BIST) technique for general sequential logic is described. This approach has been incorporated in a behavioral model synthesis system, providing automated implementation of BIST in very-large-scale-integration (VLSI) devices as well as programmable-logic-device (PLD)-based circuit packs. BIST can be directly used at all levels of testing from device testing through system diagnostics. It is based on selective replacement of existing system memory elements with BIST flip-flop cells that are connected to form a circular chain, performing data compaction and test pattern generation simultaneously. Two production VLSI devices have been implemented with this automated BIST approach. In each case, the total fault coverage was in excess of 96% and the logic overhead incurred was between 9.7 and 18.9%.< > |
| doi_str_mv | 10.1109/DAC.1988.14726 |
| format | Conference Proceeding |
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This approach has been incorporated in a behavioral model synthesis system, providing automated implementation of BIST in very-large-scale-integration (VLSI) devices as well as programmable-logic-device (PLD)-based circuit packs. BIST can be directly used at all levels of testing from device testing through system diagnostics. It is based on selective replacement of existing system memory elements with BIST flip-flop cells that are connected to form a circular chain, performing data compaction and test pattern generation simultaneously. Two production VLSI devices have been implemented with this automated BIST approach. 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In each case, the total fault coverage was in excess of 96% and the logic overhead incurred was between 9.7 and 18.9%.< ></description><subject>Built-in self-test</subject><subject>Circuit synthesis</subject><subject>Circuit testing</subject><subject>Compaction</subject><subject>Flip-flops</subject><subject>Logic devices</subject><subject>Performance evaluation</subject><subject>System testing</subject><subject>Test pattern generators</subject><subject>Very large scale integration</subject><issn>0738-100X</issn><isbn>9780818608643</isbn><isbn>0818608641</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>1988</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNp9jj0PgjAUAJuoiaisJm79A-J7QqCMiBqdZXAjDT6ghi9bGPj3GuPsdJfccoytERxECHfHKHYwFMJBL9j7E2aHgQCBwgfhe-6UWRC4YosA9zlbGPMEAA99tFgUNVwOfVvLnh78cL0lXHadbmVW8rzVvKCGtKy4oddATa8-WrWFyrgZm74ko8yKzXJZGbJ_XLLN-ZTEl60iorTTqpZ6TL9f7r_2Bvv-OX8</recordid><startdate>1988</startdate><enddate>1988</enddate><creator>Stroud, C.E.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>1988</creationdate><title>An automated BIST approach for general sequential logic synthesis</title><author>Stroud, C.E.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-ieee_primary_147263</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>1988</creationdate><topic>Built-in self-test</topic><topic>Circuit synthesis</topic><topic>Circuit testing</topic><topic>Compaction</topic><topic>Flip-flops</topic><topic>Logic devices</topic><topic>Performance evaluation</topic><topic>System testing</topic><topic>Test pattern generators</topic><topic>Very large scale integration</topic><toplevel>online_resources</toplevel><creatorcontrib>Stroud, C.E.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Stroud, C.E.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>An automated BIST approach for general sequential logic synthesis</atitle><btitle>25th ACM/IEEE, Design Automation Conference.Proceedings 1988</btitle><stitle>DAC</stitle><date>1988</date><risdate>1988</risdate><spage>3</spage><epage>8</epage><pages>3-8</pages><issn>0738-100X</issn><isbn>9780818608643</isbn><isbn>0818608641</isbn><abstract>An automated built-in self-test (BIST) technique for general sequential logic is described. This approach has been incorporated in a behavioral model synthesis system, providing automated implementation of BIST in very-large-scale-integration (VLSI) devices as well as programmable-logic-device (PLD)-based circuit packs. BIST can be directly used at all levels of testing from device testing through system diagnostics. It is based on selective replacement of existing system memory elements with BIST flip-flop cells that are connected to form a circular chain, performing data compaction and test pattern generation simultaneously. Two production VLSI devices have been implemented with this automated BIST approach. In each case, the total fault coverage was in excess of 96% and the logic overhead incurred was between 9.7 and 18.9%.< ></abstract><pub>IEEE</pub><doi>10.1109/DAC.1988.14726</doi></addata></record> |
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| identifier | ISSN: 0738-100X |
| ispartof | 25th ACM/IEEE, Design Automation Conference.Proceedings 1988, 1988, p.3-8 |
| issn | 0738-100X |
| language | eng |
| recordid | cdi_ieee_primary_14726 |
| source | IEEE Electronic Library (IEL) |
| subjects | Built-in self-test Circuit synthesis Circuit testing Compaction Flip-flops Logic devices Performance evaluation System testing Test pattern generators Very large scale integration |
| title | An automated BIST approach for general sequential logic synthesis |
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