High performance FDSOI CMOS technology with metal gate and high-k
A high performance FDSOI CMOS technology featuring metal gate electrodes and high-k gate dielectrics is presented. Work-function tuning is accomplished by materials and process modification to achieve appropriate threshold voltages for FDSOI CMOS. The gate stacks exhibit an extremely thin effective...
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| creator | Doris, B. Kim, Y.H. Linder, B.P. Steen, M. Narayanan, V. Boyd, D. Rubino, J. Chang, L. Sleight, J. Topol, A. Sikorski, E. Shi, L. Wong, L. Babich, K. Zhang, Y. Kirsch, P. Newbury, J. Walker, J.F. Carruthers, R. D'Emic, C. Kozlowski, P. Jammy, R. Guarini, K.W. Leong, M. |
| description | A high performance FDSOI CMOS technology featuring metal gate electrodes and high-k gate dielectrics is presented. Work-function tuning is accomplished by materials and process modification to achieve appropriate threshold voltages for FDSOI CMOS. The gate stacks exhibit an extremely thin effective inversion thickness (T/sub inv/) down to 14A with a gate leakage current of 0.2A/cm/sup 2/. This represents a six order of magnitude leakage reduction compared to Poly/SiO/sub 2/. By optimizing the gate stack, the highest unstrained electron mobility is realized (207cm/sup 2/A/s at E/sub eff/=1Mv/cm) at T/sub inv/=14A. Drive currents of 1050/spl mu/A//spl mu/m and 770/spl mu/A//spl mu/m at I/sub off/ of 90nA//spl mu/m and 28nA//spl mu/m are achieved for nMOS and pMOS respectively. This is the highest reported pFET drive current for metal gate transistors with high-k gate dielectrics. We also present FDSOI metal gate high-k ring oscillators and SRAM cells with static noise margin (SNM) of 328mV at V/sub dd/=1,2V. |
| doi_str_mv | 10.1109/.2005.1469272 |
| format | Conference Proceeding |
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Work-function tuning is accomplished by materials and process modification to achieve appropriate threshold voltages for FDSOI CMOS. The gate stacks exhibit an extremely thin effective inversion thickness (T/sub inv/) down to 14A with a gate leakage current of 0.2A/cm/sup 2/. This represents a six order of magnitude leakage reduction compared to Poly/SiO/sub 2/. By optimizing the gate stack, the highest unstrained electron mobility is realized (207cm/sup 2/A/s at E/sub eff/=1Mv/cm) at T/sub inv/=14A. Drive currents of 1050/spl mu/A//spl mu/m and 770/spl mu/A//spl mu/m at I/sub off/ of 90nA//spl mu/m and 28nA//spl mu/m are achieved for nMOS and pMOS respectively. This is the highest reported pFET drive current for metal gate transistors with high-k gate dielectrics. We also present FDSOI metal gate high-k ring oscillators and SRAM cells with static noise margin (SNM) of 328mV at V/sub dd/=1,2V.</description><identifier>ISSN: 0743-1562</identifier><identifier>ISBN: 4900784001</identifier><identifier>ISBN: 9784900784000</identifier><identifier>DOI: 10.1109/.2005.1469272</identifier><language>eng</language><publisher>IEEE</publisher><subject>CMOS process ; CMOS technology ; Dielectric materials ; Electrodes ; Electron mobility ; High K dielectric materials ; High-K gate dielectrics ; Leakage current ; Threshold voltage ; Tuning</subject><ispartof>Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005, 2005, p.214-215</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/1469272$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,776,780,785,786,2052,4036,4037,27902,54895</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/1469272$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Doris, B.</creatorcontrib><creatorcontrib>Kim, Y.H.</creatorcontrib><creatorcontrib>Linder, B.P.</creatorcontrib><creatorcontrib>Steen, M.</creatorcontrib><creatorcontrib>Narayanan, V.</creatorcontrib><creatorcontrib>Boyd, D.</creatorcontrib><creatorcontrib>Rubino, J.</creatorcontrib><creatorcontrib>Chang, L.</creatorcontrib><creatorcontrib>Sleight, J.</creatorcontrib><creatorcontrib>Topol, A.</creatorcontrib><creatorcontrib>Sikorski, E.</creatorcontrib><creatorcontrib>Shi, L.</creatorcontrib><creatorcontrib>Wong, L.</creatorcontrib><creatorcontrib>Babich, K.</creatorcontrib><creatorcontrib>Zhang, Y.</creatorcontrib><creatorcontrib>Kirsch, P.</creatorcontrib><creatorcontrib>Newbury, J.</creatorcontrib><creatorcontrib>Walker, J.F.</creatorcontrib><creatorcontrib>Carruthers, R.</creatorcontrib><creatorcontrib>D'Emic, C.</creatorcontrib><creatorcontrib>Kozlowski, P.</creatorcontrib><creatorcontrib>Jammy, R.</creatorcontrib><creatorcontrib>Guarini, K.W.</creatorcontrib><creatorcontrib>Leong, M.</creatorcontrib><title>High performance FDSOI CMOS technology with metal gate and high-k</title><title>Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005</title><addtitle>VLSIT</addtitle><description>A high performance FDSOI CMOS technology featuring metal gate electrodes and high-k gate dielectrics is presented. Work-function tuning is accomplished by materials and process modification to achieve appropriate threshold voltages for FDSOI CMOS. The gate stacks exhibit an extremely thin effective inversion thickness (T/sub inv/) down to 14A with a gate leakage current of 0.2A/cm/sup 2/. This represents a six order of magnitude leakage reduction compared to Poly/SiO/sub 2/. By optimizing the gate stack, the highest unstrained electron mobility is realized (207cm/sup 2/A/s at E/sub eff/=1Mv/cm) at T/sub inv/=14A. Drive currents of 1050/spl mu/A//spl mu/m and 770/spl mu/A//spl mu/m at I/sub off/ of 90nA//spl mu/m and 28nA//spl mu/m are achieved for nMOS and pMOS respectively. This is the highest reported pFET drive current for metal gate transistors with high-k gate dielectrics. We also present FDSOI metal gate high-k ring oscillators and SRAM cells with static noise margin (SNM) of 328mV at V/sub dd/=1,2V.</description><subject>CMOS process</subject><subject>CMOS technology</subject><subject>Dielectric materials</subject><subject>Electrodes</subject><subject>Electron mobility</subject><subject>High K dielectric materials</subject><subject>High-K gate dielectrics</subject><subject>Leakage current</subject><subject>Threshold voltage</subject><subject>Tuning</subject><issn>0743-1562</issn><isbn>4900784001</isbn><isbn>9784900784000</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2005</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotj0tLw0AURgdUsK0uXbmZPzDxziPzWJZobaGSRXVdJjM3D82jJAHpv7dgV9_mnAMfIU8cEs7BvSQCIE240k4YcUOWygEYqwD4LVmAUZLxVIt7spymbwABqbQLst42VU1POJbD2Pk-IN28HvIdzT7yA50x1P3QDtWZ_jZzTTucfUsrPyP1faT1RWU_D-Su9O2Ej9ddka_N22e2Zfv8fZet96zhJp1Z0JrzWCiHrggqFBqEtJYbwaFEF5xQPkBhY-HQ6qhdkCGCNspdkFJGKVfk-b_bIOLxNDadH8_H6135B1MJRl4</recordid><startdate>2005</startdate><enddate>2005</enddate><creator>Doris, B.</creator><creator>Kim, Y.H.</creator><creator>Linder, B.P.</creator><creator>Steen, M.</creator><creator>Narayanan, V.</creator><creator>Boyd, D.</creator><creator>Rubino, J.</creator><creator>Chang, L.</creator><creator>Sleight, J.</creator><creator>Topol, A.</creator><creator>Sikorski, E.</creator><creator>Shi, L.</creator><creator>Wong, L.</creator><creator>Babich, K.</creator><creator>Zhang, Y.</creator><creator>Kirsch, P.</creator><creator>Newbury, J.</creator><creator>Walker, J.F.</creator><creator>Carruthers, R.</creator><creator>D'Emic, C.</creator><creator>Kozlowski, P.</creator><creator>Jammy, R.</creator><creator>Guarini, K.W.</creator><creator>Leong, M.</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>2005</creationdate><title>High performance FDSOI CMOS technology with metal gate and high-k</title><author>Doris, B. ; Kim, Y.H. ; Linder, B.P. ; Steen, M. ; Narayanan, V. ; Boyd, D. ; Rubino, J. ; Chang, L. ; Sleight, J. ; Topol, A. ; Sikorski, E. ; Shi, L. ; Wong, L. ; Babich, K. ; Zhang, Y. ; Kirsch, P. ; Newbury, J. ; Walker, J.F. ; Carruthers, R. ; D'Emic, C. ; Kozlowski, P. ; Jammy, R. ; Guarini, K.W. ; Leong, M.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-c6611db49e9bc4cb60238817210fe9c924ac0b8db9e86d69c3cd06749172f3d33</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2005</creationdate><topic>CMOS process</topic><topic>CMOS technology</topic><topic>Dielectric materials</topic><topic>Electrodes</topic><topic>Electron mobility</topic><topic>High K dielectric materials</topic><topic>High-K gate dielectrics</topic><topic>Leakage current</topic><topic>Threshold voltage</topic><topic>Tuning</topic><toplevel>online_resources</toplevel><creatorcontrib>Doris, B.</creatorcontrib><creatorcontrib>Kim, Y.H.</creatorcontrib><creatorcontrib>Linder, B.P.</creatorcontrib><creatorcontrib>Steen, M.</creatorcontrib><creatorcontrib>Narayanan, V.</creatorcontrib><creatorcontrib>Boyd, D.</creatorcontrib><creatorcontrib>Rubino, J.</creatorcontrib><creatorcontrib>Chang, L.</creatorcontrib><creatorcontrib>Sleight, J.</creatorcontrib><creatorcontrib>Topol, A.</creatorcontrib><creatorcontrib>Sikorski, E.</creatorcontrib><creatorcontrib>Shi, L.</creatorcontrib><creatorcontrib>Wong, L.</creatorcontrib><creatorcontrib>Babich, K.</creatorcontrib><creatorcontrib>Zhang, Y.</creatorcontrib><creatorcontrib>Kirsch, P.</creatorcontrib><creatorcontrib>Newbury, J.</creatorcontrib><creatorcontrib>Walker, J.F.</creatorcontrib><creatorcontrib>Carruthers, R.</creatorcontrib><creatorcontrib>D'Emic, C.</creatorcontrib><creatorcontrib>Kozlowski, P.</creatorcontrib><creatorcontrib>Jammy, R.</creatorcontrib><creatorcontrib>Guarini, K.W.</creatorcontrib><creatorcontrib>Leong, M.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Doris, B.</au><au>Kim, Y.H.</au><au>Linder, B.P.</au><au>Steen, M.</au><au>Narayanan, V.</au><au>Boyd, D.</au><au>Rubino, J.</au><au>Chang, L.</au><au>Sleight, J.</au><au>Topol, A.</au><au>Sikorski, E.</au><au>Shi, L.</au><au>Wong, L.</au><au>Babich, K.</au><au>Zhang, Y.</au><au>Kirsch, P.</au><au>Newbury, J.</au><au>Walker, J.F.</au><au>Carruthers, R.</au><au>D'Emic, C.</au><au>Kozlowski, P.</au><au>Jammy, R.</au><au>Guarini, K.W.</au><au>Leong, M.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>High performance FDSOI CMOS technology with metal gate and high-k</atitle><btitle>Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005</btitle><stitle>VLSIT</stitle><date>2005</date><risdate>2005</risdate><spage>214</spage><epage>215</epage><pages>214-215</pages><issn>0743-1562</issn><isbn>4900784001</isbn><isbn>9784900784000</isbn><abstract>A high performance FDSOI CMOS technology featuring metal gate electrodes and high-k gate dielectrics is presented. Work-function tuning is accomplished by materials and process modification to achieve appropriate threshold voltages for FDSOI CMOS. The gate stacks exhibit an extremely thin effective inversion thickness (T/sub inv/) down to 14A with a gate leakage current of 0.2A/cm/sup 2/. This represents a six order of magnitude leakage reduction compared to Poly/SiO/sub 2/. By optimizing the gate stack, the highest unstrained electron mobility is realized (207cm/sup 2/A/s at E/sub eff/=1Mv/cm) at T/sub inv/=14A. Drive currents of 1050/spl mu/A//spl mu/m and 770/spl mu/A//spl mu/m at I/sub off/ of 90nA//spl mu/m and 28nA//spl mu/m are achieved for nMOS and pMOS respectively. This is the highest reported pFET drive current for metal gate transistors with high-k gate dielectrics. We also present FDSOI metal gate high-k ring oscillators and SRAM cells with static noise margin (SNM) of 328mV at V/sub dd/=1,2V.</abstract><pub>IEEE</pub><doi>10.1109/.2005.1469272</doi><tpages>2</tpages></addata></record> |
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| issn | 0743-1562 |
| language | eng |
| recordid | cdi_ieee_primary_1469272 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | CMOS process CMOS technology Dielectric materials Electrodes Electron mobility High K dielectric materials High-K gate dielectrics Leakage current Threshold voltage Tuning |
| title | High performance FDSOI CMOS technology with metal gate and high-k |
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