Highly scalable 90nm STI bounded twin flash cell with local interconnect

A 90nm Twin Flash memory cell with a size of 0.029/spl mu/m/sup 2//bit (3.5F/sup 2/) is presented. This cell is introduced first in a 1.8V, 2Gbit data flash. The Twin Flash technology is based on a shallow trench isolation (STI) bounded cell with local interconnect (LI) and serves for both advanced...

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Hauptverfasser: Nagel, N., Olligs, D., Polei, V., Parascandola, S., Boubekeur, H., Bach, L., Muller, T., Strassburg, M., Riedel, S., Kratzert, P., Caspary, D., Deppe, J., Wilier, J., Schulze, N., Mikolajick, T., Kusters, K.-H., Shappir, A., Redmard, E., Bloom, I., Eitan, B.
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creator Nagel, N.
Olligs, D.
Polei, V.
Parascandola, S.
Boubekeur, H.
Bach, L.
Muller, T.
Strassburg, M.
Riedel, S.
Kratzert, P.
Caspary, D.
Deppe, J.
Wilier, J.
Schulze, N.
Mikolajick, T.
Kusters, K.-H.
Shappir, A.
Redmard, E.
Bloom, I.
Eitan, B.
description A 90nm Twin Flash memory cell with a size of 0.029/spl mu/m/sup 2//bit (3.5F/sup 2/) is presented. This cell is introduced first in a 1.8V, 2Gbit data flash. The Twin Flash technology is based on a shallow trench isolation (STI) bounded cell with local interconnect (LI) and serves for both advanced code and data flash storage memories. Beyond the 90nm node the scalability of the Twin Flash device is shown for 70 and 60nm node. The 90nm technology and its scaling follow the DRAM scaling path.
doi_str_mv 10.1109/.2005.1469236
format Conference Proceeding
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source IEEE Electronic Library (IEL) Conference Proceedings
subjects Charge carrier processes
Electron traps
Flash memory cells
Hot carriers
Isolation technology
Random access memory
Scalability
Silicon compounds
Space technology
Transistors
title Highly scalable 90nm STI bounded twin flash cell with local interconnect
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