HfSiON gate dielectrics design for mixed signal CMOS
HfSiON is one of the most promising alternative gate dielectric materials for low standby power (LSTP) application. Recently, DC performance, gate leakage current, and reliability have been reported by T. Watanabe et al in 2004. However, study of analog performances of CMOS with HfSiON gate dielectr...
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| creator | Kojima, K. Iijima, R. Ohguro, T. Watanabe, T. Takayanagi, M. Momose, H.S. Tshimaru, K. Ishiuchi, H. |
| description | HfSiON is one of the most promising alternative gate dielectric materials for low standby power (LSTP) application. Recently, DC performance, gate leakage current, and reliability have been reported by T. Watanabe et al in 2004. However, study of analog performances of CMOS with HfSiON gate dielectrics is not sufficient. In this paper, we discuss 1/f noise and matching of CMOS with HfSiON gate dielectrics and predict trends in S/sub vg/ with technology scaling according to the ITRS roadmap based on Mikoshiba's model. The HfSiON dielectric condition for mixed signal CMOS were investigated. In order to satisfy 1/f noise (S/sub vg/) requirement from ITRS roadmap beyond hp65nm, the Nt must be below 1.5 /spl times/ 10/sup 17/ cm/sup -3/eV/sup -1/. The results of Vth matching were excellent even when HfSiO gate dielectric was applied to MOSFET. |
| doi_str_mv | 10.1109/.2005.1469211 |
| format | Conference Proceeding |
| fullrecord | <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_1469211</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>1469211</ieee_id><sourcerecordid>1469211</sourcerecordid><originalsourceid>FETCH-LOGICAL-i175t-4ccb69bc13706022cbbffca3ea11ae359567c51e5fd92b8dc662b3dff49705f13</originalsourceid><addsrcrecordid>eNotj7tKA0EUQAdUMImWVjbzA7veO8-dUhY1gegW0TrM404Y2ajsbKF_L2Kqw2kOHMZuEFpEcHetANAtKuME4hlbKgdgOwWA52wBVskGtRGXbFnrO4AALbsFU-u8K8MLP_iZeCo0UpynEitPVMvhg-fPiR_LNyX-p37k_fOwu2IX2Y-Vrk9csbfHh9d-3WyHp01_v20KWj03KsZgXIgoLRgQIoaQc_SSPKInqZ02NmoknZMToUvRGBFkylk5CzqjXLHb_24hov3XVI5--tmfDuUvol9Cyg</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>HfSiON gate dielectrics design for mixed signal CMOS</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Kojima, K. ; Iijima, R. ; Ohguro, T. ; Watanabe, T. ; Takayanagi, M. ; Momose, H.S. ; Tshimaru, K. ; Ishiuchi, H.</creator><creatorcontrib>Kojima, K. ; Iijima, R. ; Ohguro, T. ; Watanabe, T. ; Takayanagi, M. ; Momose, H.S. ; Tshimaru, K. ; Ishiuchi, H.</creatorcontrib><description>HfSiON is one of the most promising alternative gate dielectric materials for low standby power (LSTP) application. Recently, DC performance, gate leakage current, and reliability have been reported by T. Watanabe et al in 2004. However, study of analog performances of CMOS with HfSiON gate dielectrics is not sufficient. In this paper, we discuss 1/f noise and matching of CMOS with HfSiON gate dielectrics and predict trends in S/sub vg/ with technology scaling according to the ITRS roadmap based on Mikoshiba's model. The HfSiON dielectric condition for mixed signal CMOS were investigated. In order to satisfy 1/f noise (S/sub vg/) requirement from ITRS roadmap beyond hp65nm, the Nt must be below 1.5 /spl times/ 10/sup 17/ cm/sup -3/eV/sup -1/. The results of Vth matching were excellent even when HfSiO gate dielectric was applied to MOSFET.</description><identifier>ISSN: 0743-1562</identifier><identifier>ISBN: 4900784001</identifier><identifier>ISBN: 9784900784000</identifier><identifier>DOI: 10.1109/.2005.1469211</identifier><language>eng</language><publisher>IEEE</publisher><subject>Degradation ; Dielectrics ; Electrodes ; Fluctuations ; Hafnium ; Leakage current ; MOS devices ; MOSFETs ; Semiconductor device noise ; Signal design</subject><ispartof>Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005, 2005, p.58-59</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/1469211$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2058,4050,4051,27925,54920</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/1469211$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Kojima, K.</creatorcontrib><creatorcontrib>Iijima, R.</creatorcontrib><creatorcontrib>Ohguro, T.</creatorcontrib><creatorcontrib>Watanabe, T.</creatorcontrib><creatorcontrib>Takayanagi, M.</creatorcontrib><creatorcontrib>Momose, H.S.</creatorcontrib><creatorcontrib>Tshimaru, K.</creatorcontrib><creatorcontrib>Ishiuchi, H.</creatorcontrib><title>HfSiON gate dielectrics design for mixed signal CMOS</title><title>Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005</title><addtitle>VLSIT</addtitle><description>HfSiON is one of the most promising alternative gate dielectric materials for low standby power (LSTP) application. Recently, DC performance, gate leakage current, and reliability have been reported by T. Watanabe et al in 2004. However, study of analog performances of CMOS with HfSiON gate dielectrics is not sufficient. In this paper, we discuss 1/f noise and matching of CMOS with HfSiON gate dielectrics and predict trends in S/sub vg/ with technology scaling according to the ITRS roadmap based on Mikoshiba's model. The HfSiON dielectric condition for mixed signal CMOS were investigated. In order to satisfy 1/f noise (S/sub vg/) requirement from ITRS roadmap beyond hp65nm, the Nt must be below 1.5 /spl times/ 10/sup 17/ cm/sup -3/eV/sup -1/. The results of Vth matching were excellent even when HfSiO gate dielectric was applied to MOSFET.</description><subject>Degradation</subject><subject>Dielectrics</subject><subject>Electrodes</subject><subject>Fluctuations</subject><subject>Hafnium</subject><subject>Leakage current</subject><subject>MOS devices</subject><subject>MOSFETs</subject><subject>Semiconductor device noise</subject><subject>Signal design</subject><issn>0743-1562</issn><isbn>4900784001</isbn><isbn>9784900784000</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2005</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotj7tKA0EUQAdUMImWVjbzA7veO8-dUhY1gegW0TrM404Y2ajsbKF_L2Kqw2kOHMZuEFpEcHetANAtKuME4hlbKgdgOwWA52wBVskGtRGXbFnrO4AALbsFU-u8K8MLP_iZeCo0UpynEitPVMvhg-fPiR_LNyX-p37k_fOwu2IX2Y-Vrk9csbfHh9d-3WyHp01_v20KWj03KsZgXIgoLRgQIoaQc_SSPKInqZ02NmoknZMToUvRGBFkylk5CzqjXLHb_24hov3XVI5--tmfDuUvol9Cyg</recordid><startdate>2005</startdate><enddate>2005</enddate><creator>Kojima, K.</creator><creator>Iijima, R.</creator><creator>Ohguro, T.</creator><creator>Watanabe, T.</creator><creator>Takayanagi, M.</creator><creator>Momose, H.S.</creator><creator>Tshimaru, K.</creator><creator>Ishiuchi, H.</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>2005</creationdate><title>HfSiON gate dielectrics design for mixed signal CMOS</title><author>Kojima, K. ; Iijima, R. ; Ohguro, T. ; Watanabe, T. ; Takayanagi, M. ; Momose, H.S. ; Tshimaru, K. ; Ishiuchi, H.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-4ccb69bc13706022cbbffca3ea11ae359567c51e5fd92b8dc662b3dff49705f13</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2005</creationdate><topic>Degradation</topic><topic>Dielectrics</topic><topic>Electrodes</topic><topic>Fluctuations</topic><topic>Hafnium</topic><topic>Leakage current</topic><topic>MOS devices</topic><topic>MOSFETs</topic><topic>Semiconductor device noise</topic><topic>Signal design</topic><toplevel>online_resources</toplevel><creatorcontrib>Kojima, K.</creatorcontrib><creatorcontrib>Iijima, R.</creatorcontrib><creatorcontrib>Ohguro, T.</creatorcontrib><creatorcontrib>Watanabe, T.</creatorcontrib><creatorcontrib>Takayanagi, M.</creatorcontrib><creatorcontrib>Momose, H.S.</creatorcontrib><creatorcontrib>Tshimaru, K.</creatorcontrib><creatorcontrib>Ishiuchi, H.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Kojima, K.</au><au>Iijima, R.</au><au>Ohguro, T.</au><au>Watanabe, T.</au><au>Takayanagi, M.</au><au>Momose, H.S.</au><au>Tshimaru, K.</au><au>Ishiuchi, H.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>HfSiON gate dielectrics design for mixed signal CMOS</atitle><btitle>Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005</btitle><stitle>VLSIT</stitle><date>2005</date><risdate>2005</risdate><spage>58</spage><epage>59</epage><pages>58-59</pages><issn>0743-1562</issn><isbn>4900784001</isbn><isbn>9784900784000</isbn><abstract>HfSiON is one of the most promising alternative gate dielectric materials for low standby power (LSTP) application. Recently, DC performance, gate leakage current, and reliability have been reported by T. Watanabe et al in 2004. However, study of analog performances of CMOS with HfSiON gate dielectrics is not sufficient. In this paper, we discuss 1/f noise and matching of CMOS with HfSiON gate dielectrics and predict trends in S/sub vg/ with technology scaling according to the ITRS roadmap based on Mikoshiba's model. The HfSiON dielectric condition for mixed signal CMOS were investigated. In order to satisfy 1/f noise (S/sub vg/) requirement from ITRS roadmap beyond hp65nm, the Nt must be below 1.5 /spl times/ 10/sup 17/ cm/sup -3/eV/sup -1/. The results of Vth matching were excellent even when HfSiO gate dielectric was applied to MOSFET.</abstract><pub>IEEE</pub><doi>10.1109/.2005.1469211</doi><tpages>2</tpages></addata></record> |
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| subjects | Degradation Dielectrics Electrodes Fluctuations Hafnium Leakage current MOS devices MOSFETs Semiconductor device noise Signal design |
| title | HfSiON gate dielectrics design for mixed signal CMOS |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-04T21%3A00%3A12IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=HfSiON%20gate%20dielectrics%20design%20for%20mixed%20signal%20CMOS&rft.btitle=Digest%20of%20Technical%20Papers.%202005%20Symposium%20on%20VLSI%20Technology,%202005&rft.au=Kojima,%20K.&rft.date=2005&rft.spage=58&rft.epage=59&rft.pages=58-59&rft.issn=0743-1562&rft.isbn=4900784001&rft.isbn_list=9784900784000&rft_id=info:doi/10.1109/.2005.1469211&rft_dat=%3Cieee_6IE%3E1469211%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=1469211&rfr_iscdi=true |