AMDREL: a novel low-energy FPGA architecture and supporting CAD tool design flow
The design of a novel embedded FPGA reconfigurable hardware architecture is introduced. The architecture features a number of circuit-level low-power techniques, since power consumption is considered a primary concern. Additionally, a complete set of tools facilitating implementation of applications...
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| container_end_page | D/4 Vol. 2 |
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| creator | Soudris, D. Nikolaidis, S. Siskos, S. Tatas, K. Siozios, K. Koutroumpezis, G. Vasiliadis, N. Kalenteridis, V. Pournara, H. Pappas, I. Thanailakis, A. |
| description | The design of a novel embedded FPGA reconfigurable hardware architecture is introduced. The architecture features a number of circuit-level low-power techniques, since power consumption is considered a primary concern. Additionally, a complete set of tools facilitating implementation of applications on the proposed FPGA was presented, starting from an RTL description and producing the actual configuration bit stream. The designed full-custom FPGA is under fabrication in 0.18/spl mu/m STM CMOS technology. The prototype supports partial and dynamic reconfiguration. The efficiency of the entire system (FPGA and tools) was proven by comparisons with commercial systems. |
| doi_str_mv | 10.1109/ASPDAC.2005.1466599 |
| format | Conference Proceeding |
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Asia and South Pacific Design Automation Conference, 2005</btitle><stitle>ASPDAC</stitle><date>2005</date><risdate>2005</risdate><volume>2</volume><spage>D/3</spage><epage>D/4 Vol. 2</epage><pages>D/3-D/4 Vol. 2</pages><issn>2153-6961</issn><eissn>2153-697X</eissn><isbn>9780780387362</isbn><isbn>0780387368</isbn><abstract>The design of a novel embedded FPGA reconfigurable hardware architecture is introduced. The architecture features a number of circuit-level low-power techniques, since power consumption is considered a primary concern. Additionally, a complete set of tools facilitating implementation of applications on the proposed FPGA was presented, starting from an RTL description and producing the actual configuration bit stream. The designed full-custom FPGA is under fabrication in 0.18/spl mu/m STM CMOS technology. The prototype supports partial and dynamic reconfiguration. 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| identifier | ISSN: 2153-6961 |
| ispartof | Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005, 2005, Vol.2, p.D/3-D/4 Vol. 2 |
| issn | 2153-6961 2153-697X |
| language | eng |
| recordid | cdi_ieee_primary_1466599 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Circuits Clocks CMOS technology Design automation Energy consumption Field programmable gate arrays Hardware Prototypes Switches Tiles |
| title | AMDREL: a novel low-energy FPGA architecture and supporting CAD tool design flow |
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