Process-variation robust and low-power zero-skew buffered clock-tree synthesis using projected scan-line sampling

Zero-skew clock-tree with minimum clock-delay is preferable due to its low unintentional and process-variation induced skews. We propose a zero-skew buffered clock-tree synthesis flow and a novel algorithm that enables clock-tree optimization throughout the full zero-skew design-space by considering...

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Hauptverfasser:	Jeng-Liang Tsai, Chung-Ping Chen, C.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Algorithm design and analysis Capacitance Clocks DC generators Delay Design optimization Robustness Routing Sampling methods Wire
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