A post layout watermarking method for IP protection

We propose a new watermarking system for VLSI layout design intellectual property protection (IPP) that will not damage circuit properties. The previous studies for layout design IPP are mainly restricted to pre-layout design, i.e. they would increase layout size and vary signal timing. The idea of...

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Bibliographische Detailangaben

Hauptverfasser:	Nie, T., Kisaka, T., Toyonaga, M.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Circuits Cryptography Design methodology Information science Intellectual property Mathematics Protection Signal design Watermarking Wire
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