A one-quadrant discrete-time cellular neural network architecture for pixel-level snakes: B/W processing
This paper introduces a one-quadrant discrete-time cellular neural network architecture for the pixel-level snakes, an active-contour-based technique. The motivation behind such an architecture is to have a subsequent on-chip implementation with better figures of merit, especially area consumption a...
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| creator | Brea, V.M. Laiho, M. Vilarino, D.L. Paasio, A. Cabello, D. |
| description | This paper introduces a one-quadrant discrete-time cellular neural network architecture for the pixel-level snakes, an active-contour-based technique. The motivation behind such an architecture is to have a subsequent on-chip implementation with better figures of merit, especially area consumption and processing speed. The current paper goes through the B/W operations performed in the pixel-level snake algorithm. |
| doi_str_mv | 10.1109/ISCAS.2005.1465488 |
| format | Conference Proceeding |
| fullrecord | <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_1465488</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>1465488</ieee_id><sourcerecordid>1465488</sourcerecordid><originalsourceid>FETCH-LOGICAL-i175t-23980cf4a97cfb61bbf2191a2957ad098b4412d0a5eddb2bb17192985123bbbb3</originalsourceid><addsrcrecordid>eNotkMlOwzAURS0GiQr6A7DxD7j189DY7ErFUKkSi4JYVnbyQk3dpNgJw98TiR5d6ezO4hJyDXwCwO10uV7M1xPBuZ6AmmllzAkZCdCGgRb6lIxtYfgwaYxU-oyMuCiAKcnFBRnn_MEHlJaFmI3Idk7bBtln76rkmo5WIZcJO2Rd2CMtMcY-ukQb7JOLg7rvNu2oS-U2dFh2fUJat4kewg9GFvELI82N22G-pXfTN3pIbYk5h-b9ipzXLmYcH31JXh_uXxZPbPX8uFzMVyxAoTsmpDW8rJWzRVn7GXhfC7DghNWFq7g1XikQFXcaq8oL76EAK6zRIKQfkJfk5r8bEHFzSGHv0u_m-JP8A0b1W28</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>A one-quadrant discrete-time cellular neural network architecture for pixel-level snakes: B/W processing</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Brea, V.M. ; Laiho, M. ; Vilarino, D.L. ; Paasio, A. ; Cabello, D.</creator><creatorcontrib>Brea, V.M. ; Laiho, M. ; Vilarino, D.L. ; Paasio, A. ; Cabello, D.</creatorcontrib><description>This paper introduces a one-quadrant discrete-time cellular neural network architecture for the pixel-level snakes, an active-contour-based technique. The motivation behind such an architecture is to have a subsequent on-chip implementation with better figures of merit, especially area consumption and processing speed. The current paper goes through the B/W operations performed in the pixel-level snake algorithm.</description><identifier>ISSN: 0271-4302</identifier><identifier>ISBN: 9780780388345</identifier><identifier>ISBN: 0780388348</identifier><identifier>EISSN: 2158-1525</identifier><identifier>DOI: 10.1109/ISCAS.2005.1465488</identifier><language>eng</language><publisher>IEEE</publisher><subject>Active contours ; Cellular neural networks ; Computer architecture ; Computer science ; Data mining ; Hardware ; Information technology ; Iterative algorithms ; Pixel ; Semiconductor device modeling</subject><ispartof>2005 IEEE International Symposium on Circuits and Systems (ISCAS), 2005, p.3922-3925 Vol. 4</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/1465488$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2058,4050,4051,27925,54920</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/1465488$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Brea, V.M.</creatorcontrib><creatorcontrib>Laiho, M.</creatorcontrib><creatorcontrib>Vilarino, D.L.</creatorcontrib><creatorcontrib>Paasio, A.</creatorcontrib><creatorcontrib>Cabello, D.</creatorcontrib><title>A one-quadrant discrete-time cellular neural network architecture for pixel-level snakes: B/W processing</title><title>2005 IEEE International Symposium on Circuits and Systems (ISCAS)</title><addtitle>ISCAS</addtitle><description>This paper introduces a one-quadrant discrete-time cellular neural network architecture for the pixel-level snakes, an active-contour-based technique. The motivation behind such an architecture is to have a subsequent on-chip implementation with better figures of merit, especially area consumption and processing speed. The current paper goes through the B/W operations performed in the pixel-level snake algorithm.</description><subject>Active contours</subject><subject>Cellular neural networks</subject><subject>Computer architecture</subject><subject>Computer science</subject><subject>Data mining</subject><subject>Hardware</subject><subject>Information technology</subject><subject>Iterative algorithms</subject><subject>Pixel</subject><subject>Semiconductor device modeling</subject><issn>0271-4302</issn><issn>2158-1525</issn><isbn>9780780388345</isbn><isbn>0780388348</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2005</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotkMlOwzAURS0GiQr6A7DxD7j189DY7ErFUKkSi4JYVnbyQk3dpNgJw98TiR5d6ezO4hJyDXwCwO10uV7M1xPBuZ6AmmllzAkZCdCGgRb6lIxtYfgwaYxU-oyMuCiAKcnFBRnn_MEHlJaFmI3Idk7bBtln76rkmo5WIZcJO2Rd2CMtMcY-ukQb7JOLg7rvNu2oS-U2dFh2fUJat4kewg9GFvELI82N22G-pXfTN3pIbYk5h-b9ipzXLmYcH31JXh_uXxZPbPX8uFzMVyxAoTsmpDW8rJWzRVn7GXhfC7DghNWFq7g1XikQFXcaq8oL76EAK6zRIKQfkJfk5r8bEHFzSGHv0u_m-JP8A0b1W28</recordid><startdate>2005</startdate><enddate>2005</enddate><creator>Brea, V.M.</creator><creator>Laiho, M.</creator><creator>Vilarino, D.L.</creator><creator>Paasio, A.</creator><creator>Cabello, D.</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>2005</creationdate><title>A one-quadrant discrete-time cellular neural network architecture for pixel-level snakes: B/W processing</title><author>Brea, V.M. ; Laiho, M. ; Vilarino, D.L. ; Paasio, A. ; Cabello, D.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-23980cf4a97cfb61bbf2191a2957ad098b4412d0a5eddb2bb17192985123bbbb3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2005</creationdate><topic>Active contours</topic><topic>Cellular neural networks</topic><topic>Computer architecture</topic><topic>Computer science</topic><topic>Data mining</topic><topic>Hardware</topic><topic>Information technology</topic><topic>Iterative algorithms</topic><topic>Pixel</topic><topic>Semiconductor device modeling</topic><toplevel>online_resources</toplevel><creatorcontrib>Brea, V.M.</creatorcontrib><creatorcontrib>Laiho, M.</creatorcontrib><creatorcontrib>Vilarino, D.L.</creatorcontrib><creatorcontrib>Paasio, A.</creatorcontrib><creatorcontrib>Cabello, D.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Brea, V.M.</au><au>Laiho, M.</au><au>Vilarino, D.L.</au><au>Paasio, A.</au><au>Cabello, D.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A one-quadrant discrete-time cellular neural network architecture for pixel-level snakes: B/W processing</atitle><btitle>2005 IEEE International Symposium on Circuits and Systems (ISCAS)</btitle><stitle>ISCAS</stitle><date>2005</date><risdate>2005</risdate><spage>3922</spage><epage>3925 Vol. 4</epage><pages>3922-3925 Vol. 4</pages><issn>0271-4302</issn><eissn>2158-1525</eissn><isbn>9780780388345</isbn><isbn>0780388348</isbn><abstract>This paper introduces a one-quadrant discrete-time cellular neural network architecture for the pixel-level snakes, an active-contour-based technique. The motivation behind such an architecture is to have a subsequent on-chip implementation with better figures of merit, especially area consumption and processing speed. The current paper goes through the B/W operations performed in the pixel-level snake algorithm.</abstract><pub>IEEE</pub><doi>10.1109/ISCAS.2005.1465488</doi></addata></record> |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Active contours Cellular neural networks Computer architecture Computer science Data mining Hardware Information technology Iterative algorithms Pixel Semiconductor device modeling |
| title | A one-quadrant discrete-time cellular neural network architecture for pixel-level snakes: B/W processing |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-07T19%3A22%3A59IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=A%20one-quadrant%20discrete-time%20cellular%20neural%20network%20architecture%20for%20pixel-level%20snakes:%20B/W%20processing&rft.btitle=2005%20IEEE%20International%20Symposium%20on%20Circuits%20and%20Systems%20(ISCAS)&rft.au=Brea,%20V.M.&rft.date=2005&rft.spage=3922&rft.epage=3925%20Vol.%204&rft.pages=3922-3925%20Vol.%204&rft.issn=0271-4302&rft.eissn=2158-1525&rft.isbn=9780780388345&rft.isbn_list=0780388348&rft_id=info:doi/10.1109/ISCAS.2005.1465488&rft_dat=%3Cieee_6IE%3E1465488%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=1465488&rfr_iscdi=true |